400 Mbps串列連接收發器

Abstract

隨著積體電路製程技術的進步，對於在短距離應用中需要高頻寬和低延遲晶片之間資料傳輸也隨之增加。因此，這也導致點對點連結的廣泛使用。本論文描述一個高速串列式連結輸入輸出界面之設計。傳輸頻率定於400Mbps。 此收發器使用一個鎖相迴路作為一個時脈電路來提供多相位輸出給傳送器中的四對一多工器和接收器中的三倍超取樣頻率。這個利用充電泵浦型式的鎖相迴路包含六級差動式迴狀振盪器來提供四個相位給傳送器和十二個相位給接收器。此鎖相迴路輸入頻率為50MHz，而輸出為100MHz。在傳送器中的開汲極電流模式輸出驅動器使用電流脈衝產生電路來提供大但是短週期的電流源來增加傳送資料位元的轉變時期,也因此降低符號之間干擾影響。為了正確回復傳送的資料串，接收器採用一個數位回授控制迴路。利用三倍超取樣技巧，這個系統可以避免在兩倍超取樣追蹤系統中會遭遇的亞穩態問題。此接收器亦擁有簡單資料選取邏輯電路與數位相位移動機制的優點，因此可以減低硬體設計複雜度和增加雜訊抵抗能力。最後，接收回來的資料串被解多工成四個且每一個資料速料為100MHz的平行資料通道。 此接收器採用 0.35-μm 1P4M CMOS製程技術實現，電壓電源為3.3V。當輸出時脈為100MHz 時，量測結果顯示鎖相迴路輸出訊號的方均根抖動和峰值抖動分別為16.57ps 和120ps。

As the IC fabrication technology advances, the need for high-bandwidth and low-latency inter-chip data transfer in short-distance applications has also increased. Therefore, it has led to widespread use of point-to-point links. The thesis describes the design of a high-speed serial link I/O interface. The transmission data rate is targeted at 400Mbps. The transceiver used a phase-locked loop (PLL) as a timing circuit to provide multi-phases output for the 4-to-1 multiplexer in transmitter and 3 times oversampling in receiver. The PLL, employing charge-pump, consists of six-stage differential ring oscillator to provide four phases for the transmitter and twelve phases for the receiver. The input frequency of the PLL is 50MHz and output is 100MHz. The open-drain current mode data driver in transmitter uses current pulse generation circuits to provide large but short period current sources to enhance the transition of the transmitted data bit, therefore reducing the inter-symbol-interference effect. To recover the transmitted data stream correctly, the receiver adopts a digital feedback control loop. By using 3 times oversampling technique, the system could prevent the metastability problem in 2 times oversampling tracking system. The receiver also has the advantage of simple data selection logic and digital phase shifting mechanism, thus simplifying the hardware design and improving noise immunity. Finally, the recovered data stream is demultiplexed to the four parallel data channels, each with data rate of 100MHz. The receiver is implemented in a 0.35-μm 1P4M CMOS process and the supply voltage is 3.3V. The measured rms and peak-to-peak jitter of the 100MHz output clock of the PLL are 16.57ps and 120ps, respectively.