更小擺幅差動訊號傳輸模式之收發器

Abstract

本篇論文是設計一個應用於更小擺幅差動訊號傳輸模式之收發器，其中包含了傳送器以及擁有自動回復資料的接收器，這是一種使用很小擺幅的差動訊號（約200mV）在兩個印刷電路板或是平衡的電纜線資料傳輸的方式，我們致力於設計此收發器能操作在1.2Gbps，且此收發器是在台積電0.35um2p4m的製成下製造。 此傳送器是由虛隨機位元串列、八相位鎖相迴路、八對一多工器以及資料驅動器所組成，八相位鎖相迴路的輸入頻律為75MHz，提供八個平均分佈在150MHz的相位，其中包含的電路有相位偵測器、電荷幫浦、迴路濾波器、壓控震盪器和一個除二的除頻器。此八相位的鎖相迴路產生的平均分佈時脈提供給八對一的多工器將一組並列資料轉換成串列資料，此傳送器再將此串列資料送至傳輸線上，此電路的總功率消耗為128mW。 接收器是由一個擁有遲滯現象的比較器，三倍超取樣技術之追溯資料回復的系統所組成，其中利用比較器將小擺幅資料放大成完整擺幅資料，而追溯資料回復的系統是將資料做正確的取樣，最後此接受器會將序列資料再轉換成八個並列資料，總功率消耗為960mW。

The goal of this thesis is to design a CMOS transceiver, including a transmitter and a tracking data recovery receiver, which is based on the RSDSTM interface. RSDS stands for Reduced Swing Differential Signaling. It is a way to communicate data using a very low voltage swing (about 200mV) differentially over two printed circuit board (PCB) traces or a balanced cable. We have devoted to design a transceiver with the data rate at 1.2Gbps. And, the transceiver is fabricated in 0.35um 2P4M process. Transmitter is composed of PRBS, eight-phases PLL, 8-to-1 multiplexer and data driver. The input reference of eight phases PLL is 75MHz; it outputs a uniformly distributed 150MHz clock. The PLL is composed of Phase Detector, Charge Pump, Loop Filter, Voltage Control Oscillator and a divided-by-two. Eight phases PLL output a uniform distributed clock for multiplexer to convert parallel data to serial data. The transmitter drives the serial data on to the bus. Total power is 128mW. Receiver is composed of a comparator with hysteresis, tracking data recovery system with 3 times oversampling technique. It uses the comparator to amplify incoming small signal to full swing, and tracking data recovery system to sample data correctly. Finally, the receiver converts serial data to eight parallel data channel. Total power is 960mW.