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dc.contributor.authorLin, Dah-Jiaen_US
dc.contributor.authorLin, Chien-Chingen_US
dc.contributor.authorChen, Chih-Lungen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2014-12-08T15:16:42Z-
dc.date.available2014-12-08T15:16:42Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0582-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/12312-
dc.description.abstractThe ACS computation and the survivor memory are most power critical, consuming about 90% power in the Viterbi decoder. Based on the low power mechanisms, the scarce state transition (SST) technique and the variable truncation length, we present a Viterbi decoder for the MB-OFDM UWB applications. The SST scheme lowers state transition as well as signal switches in the ACS units. Moreover, the decoding with variable truncation length leads to the access reduction in the survivor memory. The experimental results show more than 30% power reduction under high SNRs as compared to those without SST and variable truncation length.en_US
dc.language.isoen_USen_US
dc.titleA low-power Viterbi decoder based on scarce state transition and variable truncation lengthen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Proceedings of Technical Papersen_US
dc.citation.spage99en_US
dc.citation.epage102en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000247000000025-
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