標題: | Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices |
作者: | Chen, Yin-Nien Fan, Ming-Long Hu, Vita Pi-Ho Su, Pin Chuang, Ching-Te 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Hetero-channel MOSFET;high-speed;lowpower;tunnel FET |
公開日期: | 1-十二月-2014 |
摘要: | This paper investigates the feasibility of sub-0.2 V high-speed low-power circuits with hetero-channel MOSFET and emerging Tunneling FET (TFET) devices. First, the device designs and characteristics of hetero-channel MOSFET and TFET devices are discussed and compared. Due to the significant leakage current of ultra-low V-T hetero-channel MOSFET devices, assist-circuits are required for hetero-channel MOSFET-based circuits to operate at 0.2 V. Second, the delay, dynamic energy and the Standby power of hetero-channel TFET-based and MOSFET-based logic circuits including Inverter, NAND, BUS Driver, and Latch are analyzed and evaluated. The results indicate that hetero-channel TFET-based circuits with Dual Oxide (DOX) device design to reduce the Miller capacitance provide the potential to achieve high-speed low-power operation at V-DD = 0.2 V, while the use of assist-circuits in MOSFET-based design improves the delay and dynamic energy at the expense of increased device count, circuit area, and large Standby and sleep-mode leakage power. Finally, the impacts of temperature and process variations on TFET-based and MOSFET-based logic circuits are discussed. |
URI: | http://dx.doi.org/10.1109/TCSI.2014.2335032 http://hdl.handle.net/11536/123868 |
ISSN: | 1549-8328 |
DOI: | 10.1109/TCSI.2014.2335032 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS |
Volume: | 61 |
Issue: | 12 |
起始頁: | 3339 |
結束頁: | 3347 |
顯示於類別: | 期刊論文 |