完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wu, Kai-Chiang | en_US |
dc.contributor.author | Lin, Ing-Chao | en_US |
dc.contributor.author | Wang, Yao-Te | en_US |
dc.contributor.author | Yang, Shuen-Shiang | en_US |
dc.date.accessioned | 2015-07-21T11:20:26Z | - |
dc.date.available | 2015-07-21T11:20:26Z | - |
dc.date.issued | 2014-10-01 | en_US |
dc.identifier.issn | 0278-0070 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCAD.2014.2334331 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/123975 | - |
dc.description.abstract | Power gating is an effective way to reduce leakage power. This technique uses high V-th transistors, called sleep transistors, to turn off the power supply. However, sleep transistors suffer from the bias temperature instability (BTI) effect, resulting in an increased V-th, and reduced reliability. This paper proposes two BTI-aware sleep transistor sizing algorithms to reduce the total width of sleep transistors based on the distributed sleep transistor network structure. The proposed algorithms reduce total width by more than 16.08%. More area can be reduced if the BTI effect on both sleep and cluster transistors is considered. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | BTI effect | en_US |
dc.subject | power gating | en_US |
dc.subject | reliability | en_US |
dc.title | BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCAD.2014.2334331 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | en_US |
dc.citation.volume | 33 | en_US |
dc.citation.issue | 10 | en_US |
dc.citation.spage | 1591 | en_US |
dc.citation.epage | 1595 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000344529700012 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |