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dc.contributor.authorWu, Su-Haoen_US
dc.contributor.authorWu, Jieh-Tsorngen_US
dc.date.accessioned2015-07-21T11:20:18Z-
dc.date.available2015-07-21T11:20:18Z-
dc.date.issued2014-12-01en_US
dc.identifier.issn0925-1030en_US
dc.identifier.urihttp://dx.doi.org/10.1007/s10470-014-0421-yen_US
dc.identifier.urihttp://hdl.handle.net/11536/124112-
dc.description.abstractThis paper presents an integration-leakage calibration technique for the switched-capacitor integrators in a delta-sigma modulator (DSM). Integrators realized with low-gain opamps are lossy. A DSM that uses lossy integrators exhibits a degraded signal-to-quantization-noise ratio. To calibrate an integrator, its integration leakage is detected in the digital domain, and the leakage compensation is applied to the same integrator in the analog domain. The proposed scheme can calibrate all integrators in a discrete-time DSM of any form. It can be proceed in the background without interrupting the normal DSM operation. The design considerations for the proposed calibration scheme are discussed. Design cases of a 1st-order, a 2nd-order, and a 3rd-order DSM are demonstrated and simulated.en_US
dc.language.isoen_USen_US
dc.titleBackground calibration of integrator leakage in discrete-time delta-sigma modulatorsen_US
dc.typeArticleen_US
dc.identifier.doi10.1007/s10470-014-0421-yen_US
dc.identifier.journalANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSINGen_US
dc.citation.volume81en_US
dc.citation.spage645en_US
dc.citation.epage655en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000345842200011en_US
dc.citation.woscount0en_US
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