完整後設資料紀錄
DC 欄位語言
dc.contributor.authorLin, JCen_US
dc.contributor.authorChen, SYen_US
dc.contributor.authorChen, HWen_US
dc.contributor.authorJhou, ZWen_US
dc.contributor.authorLin, HCen_US
dc.contributor.authorChou, Sen_US
dc.contributor.authorKo, Jen_US
dc.contributor.authorLei, TFen_US
dc.contributor.authorHaung, HSen_US
dc.date.accessioned2014-12-08T15:16:56Z-
dc.date.available2014-12-08T15:16:56Z-
dc.date.issued2006-04-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.45.3144en_US
dc.identifier.urihttp://hdl.handle.net/11536/12414-
dc.description.abstractIn this study, n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) having 20 and 32 angstrom gate oxide thicknesses of 0.13 mu m technology were used to investigate DC hot-carrier reliability at elevated temperatures up to 125 degrees C. The research also focused on the degradation of analog properties after hot-carrier injection. On the basis of the results of experiments, the hot-carrier degradation of I-d.op (drain current defined on the basis of analog applications) is found to be the worst case among those of three types of drain current from room temperature to 125 degrees C. This result should provide valuable insight to analog circuit designers. As to the reverse temperature effect, the substrate current (I-b) commonly accepted as the parameter for,monitoring the drain-avalanche-hot-carrier (DAHC) effect should be modified since the drain current (I-d) degradation and I-b variations versus temperature have different trends. For the devices having a gate oxide thinner than 20 angstrom, we suggest that the worst condition in considering hot-carrier reliability should be placed at elevated temperatures.en_US
dc.language.isoen_USen_US
dc.subjectdigitalen_US
dc.subjectanalogen_US
dc.subjecthot-carrieren_US
dc.subjectHCIen_US
dc.subjectreliabilityen_US
dc.subjecttemperatureen_US
dc.titleInvestigation of DC hot-carrier degradation at elevated temperatures for n-channel metal-oxide-semiconductor field-effect-transistor of 0.13 mu m technologyen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1143/JJAP.45.3144en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERSen_US
dc.citation.volume45en_US
dc.citation.issue4Ben_US
dc.citation.spage3144en_US
dc.citation.epage3146en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000237570600050-
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