元件可靠度的改善及類比電路應用時之影響

Abstract

隨者半導體工業科技的日新月異,製程技術的快速進步,使各種功能能夠同時置入於一顆晶片之中的可行性就不斷的在提升,也就是希望利用先進半導體製程來整合數位和類比功能於單一晶片中,此時對於半導體元件的可靠度除了傳統數位電路的考量,在類比電路使用時的可靠性的研究也隨之而來,. 本篇論文首先提出在深次微米元件的製程之中的回火條件控制上,時間的控制比溫度的控制更能有效改善元件熱載子的可靠性問題.當半導體深次微米製程中,源極工程用到铟(Indium)元素時,可以利用較低的溫度但較長時間的回火條件,使其均勻擴散來達到源極濃度較低, 源極電場較小進而使其有較佳熱載子的可靠性與元件特性,與此同時,當考慮系統單晶片對元件有不同功能的要求時,利用製程與元件模擬軟體的幫助及實際製程的驗證結果,適當的利用源極工程,當元件尺寸越來越小的時候,大角度的植入可以調整元件通道中二維濃度的變化,從而改變元件的各項特性,使其具有數位電路需要的大的開啟電流以及較小的靜態電流,並且同時具備類比電路的高輸出電阻和電壓增益,除此之外透過高電壓加速測試方法,來比較元件在類比電路的操作特性和傳統數位電子元件操作特性的差異之處,發現在類比電路時元件操作特性更容易有劣化的現象.進一步比較類比電路中之重要的參數不匹配特性的變化,發現NMOS的電流在遭遇高電壓後與PMOS相比,不匹配特性會有明顯劣化或變大的結果.這個現象值得提供給類比電路設計時電路設計者考慮元件劣化對參數不匹配特性的改變,因電路隨使用時間之增加而元件劣化對參數不匹配特性的改變,使得數位電路仍正常工作時,但類比電路因不匹配特性的改變而導致整個電路不能正常工作,也就造成單晶片的失效的現象.

The dissertation addresses the issues related to reliability improvement of CMOS device and reliability of CMOS device on the analog circuit application especially the mismatch degradation of devices on the analog circuit. In the beginning, the effect of post-thermal annealing after indium-halo and As-halo implantation on the reliability of sub-0.1um MOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot carrier-induced device degradation. The best results of device performance were obtained with post-annealing treatment performed at medium temperatures (e.g., 900℃) for a longer time. Secondary, MOSFETs having 20 Å and 32 Å gate oxide thickness of 0.13 μm technology are used to investigate DC hot carrier reliability at elevated temperatures up to 125℃. The research also focused on the degradation of analog properties after hot carrier injection. Based on the results of experiments, the hot carrier degradation of Id,op (defined based on analog application) is found to be the worst case from room temperature to 125℃. This result should be a valuable message for analog circuit designers. As to the reverse temperature effect, the substrate current (Ib) commonly accepted as the statues for monitoring the drain avalanche hot carrier (DAHC) effect should be modified since the drain current (Id) degradation and Ib variations versus temperature have different trends. For the devices having gate oxide thinner than 20 Å, we suggest that the worst condition in considering hot carrier reliability should be placed at elevated temperature. Finally, hot carrier stress impact on mismatch properties of n and p MOS transistors with different sizes produced using 0.13 μm CMOS technology is presented for the first time. The research reveals that HCI does degrade matching of nMOSFETs’ properties, but, for pMOSFETs, the changes are minor. Due to matching variation after HCI stress, for analog circuits’ parameters, it is found that the after stress lines of n and pMOSFETs exhibit cross points for both σ (□Vt,op) and σ (□Ids,op/Ids,op) drawings. It is suggested that the cross points can be used to indicate the minimal size for n and p pairs to have the same degree of mismatch in designing analog circuits. In addition, the interpretations for the differences in n to pMOSFETs and Ids,op to Ids,sat mismatches are provided with experimental verifications.