標題: Efficient Hardware Architecture of eta(T) Pairing Accelerator Over Characteristic Three
作者: Chung, Szu-Chi
Wu, Jing-Yu
Fu, Hsing-Ping
Lee, Jen-Wei
Chang, Hsie-Chia
Lee, Chen-Yi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Application-specific integrated circuit (ASIC) implementation;elliptic curve;eta(T) pairing
公開日期: 1-Jan-2015
摘要: To support emerging pairing-based protocols related to cloud computing, an efficient algorithm/hardware codesign methodology of eta(T) pairing over characteristic three is presented. By mathematical manipulation and hardware scheduling, a single Miller\'s loop can be executed within 17 clock cycles. Furthermore, we employ torus representation and exploit the Frobenius map to lower the computation cost of final exponentiation. Pipelining and parallelization datapath are also exploited to shorten the critical path delay. Finally, by choosing suitable multiplier architecture and selecting an appropriate number of multipliers, Miller\'s loop and final exponentiation can be computed in a fully pipelined manner. With these schemes, a test chip for the proposed pairing accelerator has been fabricated in 90-nm CMOS 1P9M technology with a core area of 1.52 x 0.97 mm(2). It performs a bilinear pairing computation over F(3(97)) in 4.76 mu s under 1.0 V supply and achieves 178% improvement to relative works in terms of area-time (AT) product. To support higher level of security, a 126-bit secure pairing accelerator that can complete a bilinear pairing computation over F(3709) in 36.2 mu s is implemented and this result is at least 31% better than relative works in terms of AT product.
URI: http://dx.doi.org/10.1109/TVLSI.2014.2303489
http://hdl.handle.net/11536/124219
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2014.2303489
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 23
起始頁: 88
結束頁: 97
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