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dc.contributor.authorLee, Xin-Ruen_US
dc.contributor.authorYang, Chih-Wenen_US
dc.contributor.authorChen, Chih-Lungen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2015-07-21T08:28:43Z-
dc.date.available2015-07-21T08:28:43Z-
dc.date.issued2015-03-01en_US
dc.identifier.issn1549-7747en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSII.2014.2368616en_US
dc.identifier.urihttp://hdl.handle.net/11536/124555-
dc.description.abstractThis brief presents an area-efficient relaxed halfstochastic nonbinary low-density parity-check (NB-LDPC) decoder. A novel decoding algorithm, namely, cumulative tracking forecast memory with concealing channel values (CTFM-CC) is proposed to reduce algorithm complexity and maintain bit-errorrate performance as well. Furthermore, the hardware complexity of variable node units (VNUs) is reduced through a truncated architecture, which only keeps the most reliable n probability density functions. To deal with the sum-product-algorithm-to-stochastic conversion of VNU, a dynamic random number generation method, which is used for sampling a stochastic symbol, is also proposed. With these features, a (168, 84) regular-(2,4) NB-LDPC code over GF(16) decoder is implemented in a 90-nm process. According to the results of postlayout simulation, this decoder can deliver a throughput of 1.13 Gb/s with a hardware efficiency of 0.90 Mb/s/K-gate at 286 MHz. Compared to related rate-1/2 NB-LDPC decoders, the proposed decoder achieves the highest hardware efficiency with similar error-correcting capability.en_US
dc.language.isoen_USen_US
dc.subjectNonbinary low-density parity-check (LDPC) codesen_US
dc.subjectrelaxed half-stochastic (RHS) algorithmen_US
dc.subjectstochastic decodingen_US
dc.titleAn Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codesen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSII.2014.2368616en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFSen_US
dc.citation.volume62en_US
dc.citation.spage301en_US
dc.citation.epage305en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000350884900018en_US
dc.citation.woscount0en_US
Appears in Collections:Articles