Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Xin-Ru | en_US |
dc.contributor.author | Yang, Chih-Wen | en_US |
dc.contributor.author | Chen, Chih-Lung | en_US |
dc.contributor.author | Chang, Hsie-Chia | en_US |
dc.contributor.author | Lee, Chen-Yi | en_US |
dc.date.accessioned | 2015-07-21T08:28:43Z | - |
dc.date.available | 2015-07-21T08:28:43Z | - |
dc.date.issued | 2015-03-01 | en_US |
dc.identifier.issn | 1549-7747 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCSII.2014.2368616 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/124555 | - |
dc.description.abstract | This brief presents an area-efficient relaxed halfstochastic nonbinary low-density parity-check (NB-LDPC) decoder. A novel decoding algorithm, namely, cumulative tracking forecast memory with concealing channel values (CTFM-CC) is proposed to reduce algorithm complexity and maintain bit-errorrate performance as well. Furthermore, the hardware complexity of variable node units (VNUs) is reduced through a truncated architecture, which only keeps the most reliable n probability density functions. To deal with the sum-product-algorithm-to-stochastic conversion of VNU, a dynamic random number generation method, which is used for sampling a stochastic symbol, is also proposed. With these features, a (168, 84) regular-(2,4) NB-LDPC code over GF(16) decoder is implemented in a 90-nm process. According to the results of postlayout simulation, this decoder can deliver a throughput of 1.13 Gb/s with a hardware efficiency of 0.90 Mb/s/K-gate at 286 MHz. Compared to related rate-1/2 NB-LDPC decoders, the proposed decoder achieves the highest hardware efficiency with similar error-correcting capability. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Nonbinary low-density parity-check (LDPC) codes | en_US |
dc.subject | relaxed half-stochastic (RHS) algorithm | en_US |
dc.subject | stochastic decoding | en_US |
dc.title | An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCSII.2014.2368616 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | en_US |
dc.citation.volume | 62 | en_US |
dc.citation.spage | 301 | en_US |
dc.citation.epage | 305 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000350884900018 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Articles |