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dc.contributor.authorKuo, PYen_US
dc.contributor.authorChao, TSen_US
dc.contributor.authorWang, RJen_US
dc.contributor.authorLei, TFen_US
dc.date.accessioned2014-12-08T15:17:02Z-
dc.date.available2014-12-08T15:17:02Z-
dc.date.issued2006-04-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2006.870417en_US
dc.identifier.urihttp://hdl.handle.net/11536/12464-
dc.description.abstractIn this letter, fully Ni self-aligned silicided (fully Ni-salicided) source/drain (S/D) and gate polycrystalline silicon thin-film transistors (FSA-TFTs) have been successfully fabricated on a 40-nm-thick channel layer. Experimental results show that the FSA-TFTs give increased ON/OFF current ratio, improved subthreshold characteristics, less threshold voltage rolloff, and larger field-effect mobility compared with conventional TFTs. The FSA-TFTs exhibit small S/D and gate parasitic resistance and effectively suppress the floating-body effect and parasitic bipolar junction transistor action. The characteristics of the FSA-TFTs are suitable for high-performance driving TFTs with good output characteristics and large breakdown voltage.en_US
dc.language.isoen_USen_US
dc.subjectfloating-body effecten_US
dc.subjectfully salicideden_US
dc.subjectparasitic bipolar junction transistoren_US
dc.subjectpolycrystalline silicon thin-film transistors (poly-Si TFTs)en_US
dc.titleHigh-performance poly-Si TFTs with fully Ni-self-aligned silicided S/D and gate structureen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2006.870417en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume27en_US
dc.citation.issue4en_US
dc.citation.spage258en_US
dc.citation.epage261en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000236519400018-
dc.citation.woscount2-
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