標題: A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
作者: Lu, Chien-Yu
Chuang, Ching-Te
Jou, Shyh-Jye
Tu, Ming-Hsien
Wu, Ya-Ping
Huang, Chung-Ping
Kan, Paul-Sen
Huang, Huan-Shun
Lee, Kuen-Di
Kao, Yung-Shin
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: 9T static random access memory (SRAM);boosted wordline;line-up write-assist (LUWA);negative bitline;subthreshold;ultralow voltage
公開日期: 1-五月-2015
摘要: This brief presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with independent single-ended read bitline and write bitline (WBL) and cross-point data-aware write structure to facilitate robust subthreshold operation and bit-interleaving architecture for enhanced soft error immunity. The design employs a variation-tolerant line-up write-assist scheme where the timing of area-efficient boosted write wordline and negative WBL are aligned and triggered/initiated by the same low-going global WBL to maximize the write-ability enhancement. A 72-kb test chip is implemented in United Microelectronics Corp. 40-nm low-power (40LP) CMOS. Full functionality is achieved for V-DD ranging from 1.5 to 0.32 V without redundancy. The measured maximum operation frequency is 260 MHz (450 kHz) at 1.1 V (0.32 V) and 25 degrees C. At 0.325 V and 25 degrees C, the chip operates at 600 kHz with 5.78 mu W total power and 4.69 mu W leakage power, offering 2x frequency improvement compared with 300 kHz of our previous 72-kb 9T subthreshold SRAM design in the same 40LP technology. The energy efficiency (power/frequency/IO) at 0.325 V and 25 degrees C is 0.267 pJ/bit, a 23.7% improvement over the 0.350 pJ/bit of our previous design.
URI: http://dx.doi.org/10.1109/TVLSI.2014.2318518
http://hdl.handle.net/11536/124832
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2014.2318518
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 23
起始頁: 958
結束頁: 962
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