標題: Investigation and Optimization of Monolithic 3D Logic Circuits and SRAM Cells Considering Interlayer Coupling
作者: Fan, Ming-Long
Hu, Vita Pi-Ho
Chen, Yin-Nien
Su, Pin
Chuang, Ching-Te
電機工程學系
Department of Electrical and Computer Engineering
公開日期: 1-Jan-2014
摘要: In this work, we comprehensively investigate the impact of interlayer coupling on monolithic 3D logic circuits and 6T SRAM cells using TCAD mixed-mode simulations. In addition to reduced interconnection length, monolithic 3D integration enables further performance enhancements with optimal layout. Our study indicates that minimum leakage, equivalent to the planar 2D circuits with dual reverse body biases, is achievable for circuits stacked in 3D fashion. Moreover, stacking NFET layer over the PFET tier facilitates larger design margins for SRAM cell stability and performance.
URI: http://hdl.handle.net/11536/124901
ISBN: 978-1-4799-3432-4
ISSN: 0271-4302
期刊: 2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
起始頁: 1130
結束頁: 1133
Appears in Collections:Conferences Paper