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dc.contributor.authorChang, Kuo-Chiangen_US
dc.contributor.authorLuo, Shien-Chunen_US
dc.contributor.authorHuang, Ching-Jien_US
dc.contributor.authorLiu, Chih-Weien_US
dc.contributor.authorChu, Yuan-Huaen_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.date.accessioned2015-07-21T08:31:16Z-
dc.date.available2015-07-21T08:31:16Z-
dc.date.issued2014-01-01en_US
dc.identifier.isbn978-1-4799-3432-4en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/124908-
dc.description.abstractThis paper presents a low-power hearing aid chip which operates under near-threshold voltage region to minimize energy consumption. The proposed variable-latency design technique compensates the performance degradation under ultra-low voltage, while the proposed FIR filter computing datapath improves the energy efficiency for filter bank computation in hearing aids. The hearing aid system composed of four heterogeneous processing elements to optimize the flexibility and power consumption. The overall system was fabricated in TSMC 65nm LP process. The measured results show that the power consumption achieves 500 mu W at 0.5V and 6 MHz.en_US
dc.language.isoen_USen_US
dc.titleAn Ultra-Low Voltage Hearing Aid Chip using Variable-Latency Design Techniqueen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)en_US
dc.citation.spage2543en_US
dc.citation.epage2546en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000346488600633en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper