適用於助聽器之低功耗數位訊號處理器

Abstract

助聽器的設計目的為擴大聲音以補償聽力障礙，現代助聽器通常透過數位技術處理聲音訊號。隨著數位技術的進步，先進的數位訊號處理得以實現日益複雜的聽損補償演算法以改善助聽器的補償效果。然而，電池容量並未隨著數位技術的進步而增加，其原因除了電池技術瓶頸外，更受限於助聽器尺寸而無法採用大尺寸、大容量的電池。因此數位訊號處理除了實現日益複雜的演算法之外，更需要減少能量消耗以增加電池的使用時間。本論文就助聽器常用的數位訊號處理提出演算法以及架構層級的設計技術。在聽損補償方面，本論文設計一套低複雜度的18頻帶1/3-octave quasi-ANSI S1.11濾波器組(filter bank)，其延遲時間限制為10 ms以符合助聽器的即時要求，並透過多率(multi-rate)結構節省93%的乘法計算。本論文亦提出一動態範圍壓縮演算法，將輸出音量的範圍壓縮在聽損導致的較小動態範圍內。透過演算法以及數字運算的最佳化，可減少90%的計算量。在3通道動態範圍壓縯的實現，亦可利用多率系統，進一步降低50%的複雜度。為了設計可程式化及低功耗的計算平台以實現聽損補償演算法，本論文開發一個異質多核心的計算平台。每個計算單元包含一個簡化的RISC處理器以及數個具特殊計算功能的硬體加速器。在助聽器計算中，該處理器的角色是控制聽損補償演算法的執行流程，硬體加速器則負責處理高運算負責度的設號處理。為了實現此一平台，本論文亦開發可變動延遲的電路設計方式。透過所提出的資料預測方法實現可變動延遲設計，助聽器可節省44%的關鍵路徑延遲時間，因此可以較低的硬體代價，使設計的電路操作於低電壓下。完整的助聽器系統整合聽損補償、雜訊抑制、以及回授消除的演算法，並且設計一個可程式化的計算平台，有效率執行助聽器演算法。該助聽器系統實現於TSMC 65nm製程，在0.5 V電壓及6 MHz頻率下，量測結果顯示聽損補償僅消耗170 µW，完整助聽器則一共消耗500 µW的功率。

Hearing aids are designed to amplify sound to compensate hearing losses. Modern hearing aids usually apply digital technology to process sound. With the improvement of digital technology, more and more sophisticated hearing loss fitting methods can be realized by advanced digital signal processing to improve quality of the compensation. However, the battery capacity does not grow with the increasing complexity of digital signal processing because of the limited physical dimension of hearing aids. Therefore, modern hearing aids also need to reduce energy consumption to extend the battery life with the improvement of signal processing. This dissertation addresses the advanced digital signal processing design of auditory compensation in both algorithmic and architectural levels. A quasi-ANSI S1.11 filter bank is presented to decompose input signals into 18 1/3-octave frequency bands. The delay of the proposed filter bank is limited under 10-ms constraint, and 93% multiplications are saved by multi-rate structure. A complexity-effective compression algorithm is addressed to squeeze the amplified signals into the reduced dynamic range of hearing losses. By algorithmic and numerical optimization, the proposed compression algorithm reduces 90% complexity. Further 50% complexity is also reduced by implementing a three-channel compression with multi-rate architecture. In order to realize the auditory compensation algorithms, a low-power and programmable computing platform is developed by integrating heterogeneous multiple processing elements. Each processing element consists of a tiny RISC processor and several specific hardwired accelerators. The RISC processor controls the algorithm flow for flexibility and the hardwired accelerators process the computation intensive tasks for energy-efficiency. To implement the platform efficiently, variable-latency design techniques are also presented. The proposed variable-latency design technique by data speculation reduces 44% critical path delay and the hearing aid computing platform can be operated under low voltage with less hardware cost. The overall hearing aid system integrates auditory compensation, noise reduction, and feedback cancellation algorithms with the proposed heterogeneous multiple processing element. The integrated system was fabricated with TSMC 65nm process, and the measured results present the auditory compensation consumes 170 µW while the overall hearing aid system consumes 500 µW under 0.5V and 6 MHz frequency.