適用於助聽器輕量化數位處理器之設計與實作

Abstract

隨著助聽器演算法的演進與開發，可程式化的需求已是趨勢。本論文提出一低功 率助聽器運算平台，處理analysis filter bank、noise reduction、wide dynamic Rangecompression、synthesis filter bank 與feedback cancellation 運算。此平台包含四個異質處理單元與共享記憶體系統，每一個處理單元包含一個精簡指令集處理器和多個低功耗特殊應用加速器，共享記憶體系統作為多處理單元資料交換的媒介。並針對有限脈衝響應濾波器運算，採用靜態浮點數運算提升訊號雜訊比與捨棄式乘法器節省硬體複雜度。依據模擬結果，相對於後捨棄式乘法，提出的基於靜態浮點數運算引擎節省28%的面積與3dB 的訊號雜訊比提升。此數位數聽器運算平台在台積電65 奈米製程(1P9M)下線。

This thesis presents a power efficient computing platform for hearing aids application included analysis filter bank, noise reduction, wide dynamic range compression synthesis filter bank and feedback cancellation, the hearing aid computing platform composes four heterogeneous processing elements and a memory subsystem. Each processing element includes one tiny RISC processor and several power-efficient hardwired accelerators. Each processing element transfer data via memory subsystem .The hardwired accelerators apply static floating-point and truncated multiplier to improve signal-to-noise ratio and reduce computational complexity. Compared to the post-truncate multiplication in FIR filter, the proposed static floating-point datapath reduces 28% area and improves 3dB SNR simultaneously. The proposed hearing aid computing platform has been fabricated in the TSMC 65nm (1P9M) technology.