適用於助聽器之低功耗聽力補償系統設計

Abstract

隨著積體電路以及訊號處理技術的快速發展，現代數位助聽器能夠大幅改善聽損者的生活品質。然而由於助聽器體積持續地縮小以及不斷地採用更多先進的訊號處理演算法來提升語音品質，其電池使用時間仍未必能讓使用者完全滿意，因此先進助聽器亟需低功耗的設計以及相對應的硬體實現來延長電池使用時間。本論文即針對助聽器的核心功能–聽力補償運算，從演算法、硬體架構、以及電路實現上來探討其低功耗的設計。助聽器聽力補償演算法通常包含二個部分：濾波器組(filter bank)以及聽力補償模組(wide-dynamic-range compression)，本論文首先提出一個18頻帶的低複雜度ANSI S1.11 1/3-octave濾波器組，利用多率(multirate)的濾波器組架構設計來節省96%的運算複雜度；而為了減少其硬體架構功耗，我們亦透過係數最佳化以及採用多種低功耗設計技巧來節省51%的功耗，此濾波器組在台積電130奈米製程下實作的功耗為87微瓦，為文獻中其他設計的30%~79%。而搭配此濾波器組，本論文亦提出一低複雜度的多率音量壓縮演算法來節省約50%的運算量，並透過數值最佳化的技巧以及設計一低雜度的音量估算方式進一步減少約90%的運算複雜度，並且不會造成可感受的音量差異。針對此音量壓縮演算法，本論文亦提出一極精簡的硬體架構並在聯電90奈米製程完成實作，其功耗為49微瓦。最後本論文所提出的濾波器組以及音量壓縮演算法已在台積電65奈米製程下進行系統整合並完成一完整之聽力補償演算法的晶片實作，其包括分析/組合(analysis/synthesis)的濾波器組以及音量壓縮模組，在24KHz取樣率的情況下，此聽力補償晶片功耗為177微瓦，相較於目前一般助聽器設計，可節省約四分之三的數位訊號處理功耗；而在電流量方面，假設電壓轉換器效率為50%，則其電流為354微安培，亦較一般助聽器電流規格減少約30%。

Based on the quickly advancing IC and signal processing technologies, digital hearing aids nowadays can significantly improve the living quality of the hearing-impaired people. However, the battery usage times are behind expectations all the time due to the small form factor and the continual integration of more sophisticated signal processing algorithms. In other words, modern hearing aids need low-power design and implementation techniques urgently. In this dissertation, low-power optimizations of the core function in a digital hearing aid – the auditory compensator, which is usually composed of a filter bank and a wide-dynamic-range compressor (WDRC), are addressed from algorithm, architecture, to circuit levels. First, an 18-band complexity-effective ANSI S1.11 1/3-octave filter bank is proposed with a multirate structure to save 96% computations. The power consumption is further saved by 51% with coefficient optimization and various low-power architecture and circuit techniques. The chip implementation with the TSMC 130nm technology consumes only 87μW, which is only 30%~79% of comparative designs. Then, a multirate WDRC is designed for our proposed filter bank accordingly to save about 50% computations. A low-complexity level estimator together with aggressive numerical optimizations can further reduce 90% WDRC computations without audible artifacts. The silicon implementation in the UMC 90nm technology consumes 49μW power only. Finally, a complete auditory compensator, including an analysis filter bank, WDRC, and a synthesis bank, has been integrated and fabricated using the TMSC 65nm technology. The chip consumes 177μW only, which is four-times more energy efficient than the auditory compensators in modern digital hearing aids. The current dissipation of the proposed auditory compensator is 354μA based on assumption of the 50% efficiency of typical DC-DC converter. This current drain is also 30% less than that of the modern hearing aids.