標題: Power-Rail ESD Clamp Circuit with Embedded-Trigger SCR Device in a 65-nm CMOS Process
作者: Altolaguirre, Federico A.
Ker, Ming-Dou
電機學院
College of Electrical and Computer Engineering
公開日期: 1-Jan-2014
摘要: SCR is the preferred ESD protection device in nanoscale CMOS technologies due to the better area efficiency compared the BIGFET, virtually no leakage current and smaller capacitance. The main drawback of the SCR is the slow turn-on speed, which is solved by adding dummy gates to block the STI formations inside the SCR structure. This work demonstrates that the dummy gate inside the SCR can be effectively used as an embedded trigger transistor, eliminating the need of an external trigger transistor in the ESD protection circuit and so further reducing silicon area and standby leakage current.
URI: http://hdl.handle.net/11536/124996
ISBN: 978-1-4799-4132-2
ISSN: 1548-3746
期刊: 2014 IEEE 57TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)
起始頁: 250
結束頁: 253
Appears in Collections:Conferences Paper