標題: A Read-Write Aware DRAM Scheduling for Power Reduction in Multi-Core Systems
作者: Lai, Chih-Yen
Pan, Gung-Yu
Kuo, Hsien-Kai
Jou, Jing-Yang
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Jan-2014
摘要: The demand of high performance and low power has increased the importance of power efficiency in multi-core systems. In modern multi-core architectures, DRAM has dominated the power consumption and therefore reordering based DRAM scheduling has been intensively studied to reduce the power. However, the benefit of reordering is not fully explored by the previous studies. To further reduce the power, this paper proposes the read-write reordering and the read-write aware throttling. When compared to the existing work, the proposed techniques reduce 10% more DRAM power with less performance degradation.
URI: http://hdl.handle.net/11536/125048
ISBN: 978-1-4799-2816-3
ISSN: 2153-6961
期刊: 2014 19TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)
起始頁: 604
結束頁: 609
Appears in Collections:Conferences Paper