| Title: | DESIGN OF 2xV(DD) LOGIC GATES WITH ONLY 1xV(DD) DEVICES IN NANOSCALE CMOS TECHNOLOGY |
| Authors: | Chiu, Po-Yen Ker, Ming-Dou 電機學院 College of Electrical and Computer Engineering |
| Issue Date: | 1-Jan-2013 |
| Abstract: | The novel 2xV(DD) NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1xV(DD) devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2xV(DD) tolerant capability. Thus, the new 2xV(DD) logic gates can be operated under 2xV(DD) voltage environment without suffering the gate-oxide reliability issue. |
| URI: | http://hdl.handle.net/11536/125063 |
| ISBN: | 978-1-4799-1166-0 |
| ISSN: | 2164-1676 |
| Journal: | 2013 IEEE 26TH INTERNATIONAL SOC CONFERENCE (SOCC) |
| Begin Page: | 33 |
| End Page: | 36 |
| Appears in Collections: | Conferences Paper |
- Design of 2 x V-DD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 x V-DD Thin-Oxide Devices / Ker, Ming-Dou;Chiu, Po-Yen
- Design of mixed-voltage I/O buffer by using NMOS-blocking technique / Ker, Ming-Dou;Chen, Shih-Lun
- THE ANALYSIS AND DESIGN OF CMOS MULTIDRAIN LOGIC AND STACKED MULTIDRAIN LOGIC / WU, CY;WANG, JS;TSAI, MK
- High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process / Ker, Ming-Dou;Lin, Chun-Yu
- A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications / Tseng, YK;Wu, CY
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