Design of 2 x V-DD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 x V-DD Thin-Oxide Devices

Abstract

A new 2 x V-DD-tolerant input/output (I/O) buffer with process, voltage, and temperature (PVT) compensation is proposed and verified in a 90-nm CMOS process. Consisting of the dynamic source bias and gate controlled technique, the proposed mixed-voltage I/O buffer realized by only 1xV(DD) devices can successfully transmit and receive 2 x V-DD signal. Utilizing this technique with only 1xV(DD) devices, the digital logic gates are also modified to have 2xV(DD)-tolerant capability. With 2xV(DD)-tolerant logic gates, the PVT variation detector has been implemented to detect PVT variations from 2 x V-DD signal and provide compensation control to the 2 x V-DD-tolerant I/O buffer without suffering the gate-oxide overstress issue.