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dc.contributor.authorLu, Chien-Yuen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2015-07-21T08:30:58Z-
dc.date.available2015-07-21T08:30:58Z-
dc.date.issued2013-01-01en_US
dc.identifier.isbn978-1-4799-1166-0en_US
dc.identifier.issn2164-1676en_US
dc.identifier.urihttp://hdl.handle.net/11536/125070-
dc.description.abstractThis paper presents a novel subthreshold 9T SRAM cell with row-based Word-Line (WL) and column-based data-aware Write Word-Lines (WWLs). The decoupled Read port and cross-point Write structure provide a disturb-free cell and facilitate bit-interleaving architecture to improve soft error immunity. Compared with a previous cross-point Write 9T subthreshold SRAM cell reported in the literature, the proposed 9T SRAM cell offers comparable stability with improved Read performance and variation-tolerance. Monte Carlo simulations based on UMC 40nm Low-Power (40LP) technology indicate that the BL access time improves by 15.35% to 17.37%, and the variation (sigma of BL access time) improves by 5.12% to 9.22% for V-DD ranging from 0.3V to 0.6V. Based on a 72Kb SRAM macro design in UMC 40LP process, the proposed 9T cell achieves about 9% better chip access time (Ta) at SS corner for V-DD ranging from 0.3V to 0. 45V.en_US
dc.language.isoen_USen_US
dc.titleA Disturb-Free Subthreshold 9T SRAM Cell With Improved Performance and Variation Toleranceen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2013 IEEE 26TH INTERNATIONAL SOC CONFERENCE (SOCC)en_US
dc.citation.spage325en_US
dc.citation.epage329en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000351736000050en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper