An LDPC Decoder with SNR Information

Abstract

In this work an LDPC decoder which complies with IEEE 802.11n is proposed and implemented. The code rate is 1/2 and the code length is 648. We used partially parallel structure to reduce the area. Additionally the SNR information is applied to improve the BER performance. Moreover the CNU and the BNU in the min-sum-correct algorithm were reordered so that the hardware complexity can be reduced, and early termination can be achieved at the first iteration. Furthermore the parity check matrix is reordered such that the latency of each iteration is reduced by 1/3. The proposed LDPC decoder can reach a throughput of 37 similar to 319Mbps with a core area of 5.3 mm(2) and power consumption 224mW in a TSMC 90nm process.