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dc.contributor.authorChung, SSen_US
dc.contributor.authorYeh, CHen_US
dc.contributor.authorFeng, HJen_US
dc.contributor.authorLai, CSen_US
dc.contributor.authorYang, JJen_US
dc.contributor.authorChen, CCen_US
dc.contributor.authorJin, Yen_US
dc.contributor.authorChen, SCen_US
dc.contributor.authorLiang, MSen_US
dc.date.accessioned2014-12-08T15:17:09Z-
dc.date.available2014-12-08T15:17:09Z-
dc.date.issued2006-03-01en_US
dc.identifier.issn1530-4388en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TDMR.2006.871415en_US
dc.identifier.urihttp://hdl.handle.net/11536/12521-
dc.description.abstractFor the first time, a shallow trench isolation (STI)-induced enhanced degradation in pMOSFETs for ultrathin gate oxide devices has been observed. The ID degradation is enhanced as a reduction in the gate width and the hot carrier (HC) or negative bias temperature instability (NBTI) effect. Extensive studies have been compared for atomic layer deposition (ALD)-grown and plasma-treated oxide pMOSFETs. Different temperature dependences were observed. At room temperature, hole trap is dominant for the device degradation, in which holetrap-induced V-T is significant, whereas at high temperature under NBTI stress, interface trap becomes more significant, which dominates the device ID degradation. In addition, the V-T rolloff can be modeled as a width narrowing effect specifically for STI. More importantly, the NBTI-induced interface/oxide traps are strongly related to the hydrogen and N-2 content in the gate oxide formation process. The interface trap generation is suppressed efficiently using the ALD-grown gate oxide. These results provide a valuable guideline for the understanding of the HC and NBTI reliabilities in an advanced ALD-grown gate oxide processes/devices.en_US
dc.language.isoen_USen_US
dc.subjectatomic layer deposition (ALD)en_US
dc.subjectgate stacken_US
dc.subjectnarrow-width effecten_US
dc.subjectnegative bias temperature instability (NBTI)en_US
dc.subjectshallow trench isolation (STI)en_US
dc.titleImpact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stacken_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TDMR.2006.871415en_US
dc.identifier.journalIEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITYen_US
dc.citation.volume6en_US
dc.citation.issue1en_US
dc.citation.spage95en_US
dc.citation.epage101en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000236944800014-
dc.citation.woscount7-
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