Sub-nW 5-GHz receiver front-end circuit design

doi:10.1109/SMIC.2007.322821

Full metadata record

DC Field	Value	Language
dc.contributor.author	Hsu, Tatao	en_US
dc.contributor.author	Liu, Yen-Lin	en_US
dc.contributor.author	Yen, Shu-Hui	en_US
dc.contributor.author	Kuo, Chien-Nan	en_US
dc.date.accessioned	2014-12-08T15:17:11Z	-
dc.date.available	2014-12-08T15:17:11Z	-
dc.date.issued	2007	en_US
dc.identifier.isbn	978-0-7803-9764-4	en_US
dc.identifier.uri	http://hdl.handle.net/11536/12534	-
dc.identifier.uri	http://dx.doi.org/10.1109/SMIC.2007.322821	en_US
dc.description.abstract	In this work a 5-GHz receiver front-end is designed for the application of wireless sensor networks. The circuit topology is chosen available for low supply voltage below 1V The stability condition of the LNA circuit is ensured by adding reactive components. Total power consumption of the fabricated circuit is 0.86mW, of which 0.7mW goes to the LNA stage. The measured return loss and conversion gain are 11dB and 25dB, respectively. The noise figure is 12dB and the IIP3 is around -6.5dBm.	en_US
dc.language.iso	en_US	en_US
dc.subject	low power design	en_US
dc.subject	low-noise amplifier	en_US
dc.subject	single-balanced mixer	en_US
dc.title	Sub-nW 5-GHz receiver front-end circuit design	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.doi	10.1109/SMIC.2007.322821	en_US
dc.identifier.journal	2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Digest of Papers	en_US
dc.citation.spage	205	en_US
dc.citation.epage	208	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.identifier.wosnumber	WOS:000245461300052	-
Appears in Collections:	Conferences Paper

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