USB3高速測試載板之通道設計與分析

Abstract

IC(Integrated Circuit)的製程技術演進，終端應用的速度也不斷地提昇；在運作速度越來越快的情形下，半導體測試領域對於時序與雜訊的要求也亦趨嚴格，在ATE測試架構上，由於機台限制，訊號傳遞路徑需經過層層轉接；這些環節在電性測試時所帶來的寄生效應，在現今的高速測試要求下已足以影響結果成敗。

訊號能以正確的時序和電壓在電路中傳遞並做出回應的能力，稱為訊號完整性(Signal Integrity 簡稱 SI)，對於高速的傳輸介面應用，外來雜訊、電源干擾、阻抗的不匹配等都可能造成SI問題使系統不穩定；本論文研究透過訊號完整性分析和電磁模擬佈局結果，估算出系統餘裕並改善頻寬，設計出可符合高速訊號測試需求之載板，以確保測試系統能以全速穩定運作。

本文研究以訊號完整性之考量前提下，設計符合頻寬需求之高速載板，PCB設計使用Cadence Allegro 佈局軟體，電磁模擬軟體使用Ansys SIwave、HFSS & Nexxim，分別進行時域與頻域分析，用以調整佈局設計，實驗模擬結果顯示USB3高速載板得到顯著的信號完整性改善並符合規格。

The evolution of IC (Integrated Circuit) process technology has equipped the end users higher speed in application. With the operation speed growing faster and faster, the expectation for signal timing and noise reduction in semiconductor testing field are also getting higher. Due to the mechanical restrictions of ATE testing architecture, the signal must be transmitted via more complicated paths, these factors will cause the electrical parasitic effect and affect the results of the high-speed functional testing.

Signal Integrity (SI) presents the response ability of signal timing and leveling for the circuit. For the high speed transmitting applications, noise, power interferences and impedance mismatch issues may cause SI problems and make the whole system unstable. This thesis provides a methodology to evaluate and improve the bandwidth of system via SI analysis and electromagnetic simulation. We need to design such load boards which can meet the high speed testing requirements, and we ensure that the testing system is up and running stably by full speed.

Under the premise for the SI considerations of this work, we design a high-speed load board which meets the bandwidth requirements. We use Cadence Allegro for PCB design, Ansys SIwave、HFSS & Nexxim for time and frequency domain analysis, and we adjust the layout design according to simulation results. Based on the aforementioned results, we can improve SI issues significantly and meet the requirements in USB3.