先進記憶元件製程可靠性改善之研究

Abstract

隨著科技的發展，半導體已在日常生活中被廣泛的應用，而記憶體元件的發明，提供了記憶及隨機存取等功能，更讓許多電子產品的便利性大幅提升。但記憶體元件的製作比起一般半導體邏輯製程對於製程上的要求更為嚴謹，尤其是製程中的污染物等缺陷與會導致元件失效，可靠度及良率降低。為了避免記憶體元件與邏輯區的漏電流產生，利用氮化矽（Si3N4）的薄膜蝕刻製作其絕緣層，以確保其可靠性，但製程中卻衍生聚合物殘留（Polymer Residues）的問題，而導致可靠度及良率降低。本論文研究提出二種方法改善此一殘留缺陷，進而提升晶圓元件品質、可靠度及良率。 在氮化矽薄膜經過電漿蝕刻的離子轟擊之後，所裸露出來的氧化層表面會變得粗糙，而在後續的洗淨過程當中，粗糙的表面易沾黏洗淨槽中的聚合物而形成缺陷殘留。第一種改善方法是改良電漿灰化程式，利用氧電漿對於被破壞的氧化層進行修補作用，讓粗糙度降低，避免聚合物的沾黏；第二種方法是改善蝕刻後的潔淨步驟，將原本使用SPM的洗淨製程改為SPM後再加上APM酸，即使晶圓已經產生聚合物的缺陷，也可以利用APM酸當中的化學機制移除了原本聚合物回沾表面的缺陷。

With the development of semiconductor science and technology, various devices have been widely used in our daily life. The invention of memory components, providing functions such as memory and random-access, facilitates the electronic products more convenience. Several processes for flash memory and logic devices are complicate. The polarity control is especially difficult for the manufacturing level which requires significant strictly process control. In order to avoid memory leakage problem, the use of silicon nitride (Si3N4) spacer design enhances its insulation behavior and ensures device reliability. However, the adsorption of polymeric residue degrades the reliability and reduces the manufacturing yield. This study aims to develop two methods to avoid the residual defects and improve manufacturing quality, reliability and yield of wafers. After plasma etching from ion bombardment, the exposed layer of oxide on the surface will exhibit roughness. Roughly surface will adsorb polymer residue defects from the traditional clean tank system. In addition, the use of O2 plasma restores the intact of pre-damage oxidation layer. Therefore, this mean decreases the rough problem. Moreover, the use of sequencial SPM and APM, instead of only SPM, is another effective way to remove polymer like defects.