固相磊晶及準分子雷射結晶應用於低溫多晶鍺薄膜電晶體之研究

Abstract

在三維積體電路(three-dimension integrated circuited)的發展中，單片疊層(monolithic stacking)技術因其極佳的曝光對準度而可獲得最高之堆疊元件密度，故受到廣泛的討論。而此技術主要的挑戰在於如何在不影響下層元件特性下之低溫製程下製備高品質的上層薄膜以製備高性能元件。其中具有低溫製程、高薄膜結晶品質等優勢的低溫多晶矽(LTPS)技術即符合上述的要求。另一方面，為了進一步提升此種方法所製備之電晶體特性以應用於三維積體電路，使用擁有更高載子遷移率(mobility)、低熔點等優點的鍺(germanium) 以取代傳統使用的矽(silicon)做為上層半導體材料則具有相當大之潛力。在本論文中我們將針對不同方式所製備的低溫多晶鍺薄膜進行詳細研究，並嘗試製備出高性能的多晶鍺薄膜電晶體。 本論文分別探討透過固相結晶(solid-phase crystallization)技術及準分子雷射結晶(excimer-laser crystallization)技術製備出高品質多晶鍺薄膜。前者的晶粒大小可達約300奈米，而後者更可達到1.4微米以上。並將晶界控制技術(location-controlled grain boundary)應用於多晶鍺薄膜製備上，成功獲得單一垂直通道之晶界，位於通道區(recessed region)之正中央處的結果。 在實際製備p型多晶鍺薄膜電晶體並進行電性分析的部分，透過固相結晶技術所製備之多晶鍺薄膜電晶體表現出極差的開關電流比(on/off current ratio)特性和極大的漏電流，其開關電流比僅有1.2倍。雖然透過準分子雷射技術所製備之多晶鍺薄膜電晶體可獲得改善，然其最大開關電流比亦僅有5.7倍。其開關特性不佳乃因多晶鍺薄膜本身具有高濃度電洞與本論文所製作之p-型薄膜電晶體所使用之 p+ 源閘極接面形成一個類電阻之形態所導致，而此電洞的來源主要為分佈於鍺晶界位置的類受體空缺 (acceptor-like vacancies)。而電洞濃度在經過準分子雷射改善薄膜結晶品質後有大幅降低的趨勢所以可獲得較佳之電晶體特性，此種現象可由其通道電阻值之變化加以說明。鍺薄膜本身具有高濃度電洞的現象與傳統的多晶矽差異甚大，解決此問題成為達成製備高性能鍺薄膜電晶體的主要因素。

The monolithic stacking was widely investigated because of the best alignment between the device levels and thus the highest device density for the three-dimensional integrated circuits (3D-ICs). Nevertheless, the major challenges for the monolithic stacking were to fabricate a high quality top active layer on the insulator with the low thermal budget to prevent the under-layered from the thermal degradation. The low-temperature polycrystalline-silicon (LTPS) technology has been employed as a suitable approach to achieve this goal. On the other hand, germanium (Ge) has the advantages of much higher carrier mobility and lower melting point than the silicon (Si) and could be expected to further promote the electrical properties of 3-D ICs. In this thesis, polycrystalline germanium (poly-Ge) thin films via various low temperature crystallization methods would be investigated in detail and poly-Ge thin film transistors (TFTs) would be fabricated and characterized. Solid-phase crystallization (SPC) and excimer-laser crystallization (ELC) have been utilized to achieve the high quality poly-Ge thin films. The grain size of poly-Ge thin films could reach about 300 nm for the SPC one and 1.4 µm for the ELC one. Furthermore, the location-controlled grain boundary technology via the ELC has been conducted on the poly-Ge thin films to achieve the high quality crystallization. A single grain boundary perpendicular to the channel direction could be successfully allocated at the center of the channel region. For the poly-Ge TFT characteristics, p-channel poly-Ge TFTs via the SPC attained poor on/off current ratio of only 1.2 and a high drain leakage current. Although the poly-Ge TFTs via the ELC could be slightly improved, the on/off current ratio was still only 5.7. The possible reason of the poor performance was ascribed to the high hole concentration in the poly-Ge thin films, resulting from the acceptor-like vacancies in the grain boundaries. Therefore, the interface between the p+ source/drain and the channel region of the p-channel TFTs in this thesis demonstrated an electrical properties like a resistor. The hole concentration of poly-Ge thin films significantly decreased after the ELC because of the improvement of the crystallization quality, which could be proven from the channel resistance measurement and led to a better on/off current ratio. The phenomenon of acceptor-like vacancies in the Ge grain boundaries is quite different from the case of the poly-Si thin films. Therefore, it is a key issue for poly-Ge TFTs to control the hole concentration from the Ge grain boundaries.