元件參數萃取與解析式模型以探討奈米CMOS元件佈局效應對於直流與高頻特性影響

Abstract

在本論文中，各式元件佈局將會被使用以探討佈局效應對於奈米元件特性的影響。為了達到更高的最大震盪頻率與更低的高頻雜訊，同時變化閘指寬度與閘指數目的多閘指元件，其可以有效地降低閘極電阻，因此已經被廣泛使用於現今的射頻電路設計。然而，持續微縮閘指寬度的多閘指元件會面臨來自淺溝槽隔離層的應力影響，使電子等效遷移率降低，最終導致轉導下降。再者，來自閘指尾端的雜散電容也會使總閘極電容隨著閘指數目上升而顯著上升。 為了可靠地驗證淺溝槽隔離層應力與等效摻雜濃度對於電子等效遷移率的影響，精確萃取電子等效遷移率必須將源極金屬連線產生的電阻、等效總通道寬度、閘極長度等因子一併納入考量。源極金屬連線產生的電阻可利用我們已建立的傳輸線模型計算得到，計算結果顯示當閘指數目增加與閘指寬度減少，會使源極金屬連線變得窄又長，導致源極電阻上升。如果沒有進行源極電阻的校正，將會低估電子等效遷移率。至於閘極長度與等效總通道寬度，它們可以利用我們的高精確電容方法為基礎之專利「半導體元件之參數萃取方法」萃取得之。為了降低源極電阻與淺溝槽隔離層產生的應力，本論文提出了兩種新式元件佈局，即MG元件與MR元件。 除了電子等效遷移率之外，佈局效應對於門檻電壓與汲極導致位障降低的影響也會被探討。我們的實驗結果顯示，相較於其他多閘指元件，有最大橫向淺溝槽隔離層應力的SF元件有最高的門檻電壓。此結果表示，越大的淺溝槽隔離層應力會導致硼原子擴散減緩。關於汲極導致位障降低，本論文的實驗結果顯示，越窄的閘指寬度會得到其被抑制的優點，此一結果是來自於汲極至閘極延伸區的雜散電容。在第三章，我們提出一個考量上述效應的新式解析式門檻電壓模型，以預測閘指寬度微縮對於汲極導致位障降低的影響。另一方面，硼原子擴散減緩不只造成門檻電壓上升，也會使源極與閘極重疊區長度(LSDE)變短。本論文第四章已建立一新方法，以精確地萃取此一元件參數LSDE，並且驗證我們的論點。 最後，第五章將會分析探討佈局效應對於元件高頻特性如截止頻率與最大震盪頻率的影響。利用傳統Y-method所萃取之閘極電阻顯示出不正常的佈局效應。此結果表示，四端電晶體所造成之不可忽略的寄生元件如源極電阻與電感，必須被考量進閘極電阻的萃取方法。一個適用於四端電晶體的閘極電阻萃取方法成為未來有趣且富有挑戰性的研究主題。關於截止頻率與最大震盪頻率，我們研究發現，高閘指數目與窄閘指寬度的多閘指元件雖然可以降低閘極電阻，即使在某些例子裡，降低的閘極電阻可以改善最大震盪頻率，但也會造成總閘極電容顯著上升，因此通常會劣化截止頻率，甚至進一步影響最大震盪頻率。因此，仍需要投入更多的研究工作在最佳化元件佈局。

In this thesis, the impacts of the layout dependent effects on the nanoscale device performances, will be investigated in a variety of the device layouts. In order to achieve the higher maximum oscillation frequency (fMAX) and the lower RF noise, the multi-finger (MF) devices with the simultaneously varied finger width (WF) and finger number (NF), for an effective reduction of gate resistance (Rg), have been widely adopted in the modern RF circuit designs. However, the multi-finger devices with the continuous scaling of WF will suffer the undesired increase of the compressive stress from STI, which leads to the lower effective electrons mobility (ueff) and thereby the lower transconductance (gm). Moreover, the increase of NF will result in the increase of the total gate capacitance (Cgg) due to the poly-finger-end fringing capacitance (Cf(poly-end)). To facilitate a reliable verification of the impact from the STI stress and other layout dependent effects like effective doping concentration on eff, an accurate extraction of the source line resistance (RS), the effective channel width (Weff), and the gate length (Lg) is mandatory to realize accurate eff extraction. The RS can be calculated by our developed distributed transmission line (TML) model, and the results indicate that the larger NF and narrower WF leads to the higher RS due to the narrower and longer source line. Without taking RS into account will lead to underestimate of the extracted eff. As for Lg and Weff, they can be extracted by using our proprietary high precision capacitance method based US patent 8,691,599 B2「Parameter Extraction Method for Semiconductor Device」. To reduce RS and STI transverse stress, there are two new layouts, such as multi-group (MG) and multi-ring (MR) devices, proposed and implemented in this thesis. In addition to eff, the layout dependent threshold voltage (VT) and drain induced barrier lowering (DIBL) have been investigated as well. In our experimental, the single-finger (SF) devices with the largest lateral STI stress reveal much higher VT than all MF devices, and it suggests the retardation of boron diffusion caused by the compressive stress. Regarding DIBL, the experimental results indicate that the narrower WF will bring about the benefit of the suppression of DIBL due to the corner fringing field coupling from the drain to the poly-gate extension. In Chapter 3, a new analytical VT model incorporating 3-D DIBL effect has been developed to predict the WF scaling effects in DIBL. Furthermore, the suppressed boron diffusion may reduce the source/drain extension (SDE) overlap length (LSDE). In Chapter 4, This influence of layout dependent stress on LSDE has be verified and proven by our new method for an accurate extraction of LSDE and RSDE. Finally, in Chapter 5, the layout dependent effects in high frequency characteristics such as the cut-off frequency (fT) and fMAX will be demonstrated and investigated. The abnormal layout dependence revealed in the Rg extracted by the conventional Y-method suggests that the non-negligible parasitic elements like RS and the source inductance (LS) in a 4-terminal (4T) MOSFET should be taken into account. An improved Rg extraction method to be valid for 4T MOSFETs becomes an interesting and challenging work in the future. Regarding fT and fMAX, it is found that the larger NF and smaller WF intended to reduce Rg generally leads to lower fT, due to a significant increase of Cgg, and further impact on fMAX , even if the reduced Rg may improve fMAX in some cases. Thus, the solutions for the optimized device layouts deserve an extensive research efforts in the future.