連續波雷射結晶製備應變多晶矽奈米線三閘極薄膜電晶體之研究

Abstract

近年來低溫多晶矽薄膜電晶體已被廣泛應用於主動式平面顯示器，因為其相對於傳統非晶矽薄膜電晶體擁有較優異的載子遷移率、低功耗，而過去將非晶矽薄膜結晶的技術有固相結晶法(Solid Phase Crystallization)、金屬誘導結晶法（Metal-Induced Crystallization）、金屬誘導橫向結晶法(Metal-Induced Lateral Crystallization)、準分子雷射結晶（Excimer Laser Crystallization）以及連續波雷射結晶(Continuous Wave Laser Crystallization)等。其中以連續波雷射結晶之技術能夠達到最大的晶粒尺寸，同時此薄膜亦有極佳之結晶性和平順的表面粗糙度，因此所製備之薄膜電晶體能夠擁有優異電特性以及可靠度之表現，此外亦有研究指出，透過連續波雷射結晶之多晶矽薄膜中存在著雙軸伸張應變，此應變對於載子遷移率有增強之作用。而本研究為了有效抑制通道中晶粒邊界(Grain Boundaries)對元件電性造成之弱化影響，因此利用側壁間隙壁之技術(Spacer Technology)製備奈米線三閘極結構之電晶體以觀察到此效應，進而提升連續波雷射結晶多晶矽薄膜電晶體之電特性。 本論文分為兩部分，首先藉由材料分析連續波雷射製成的多晶矽薄膜其縱向固化的超大晶粒區域，實驗結果顯示此區域內之晶粒大小約為2微米*20微米、表面粗糙度約為 2.829 nm、擁有良好的結晶性、並存在強度約為800 MPa的雙軸伸張應變。在另一方面，亦發現當薄膜被蝕刻成奈米線後原本存在於薄膜之中的雙軸伸張應變，會傾向只存在單軸之伸張應變。 在電性探討部份，我們分別比較連續波雷射製成的N型多晶矽平面式以及三閘極奈米線薄膜電晶體，其載子遷移率分別為625 cm2V-1s-1和825 cm2V-1s-1，而次臨界擺幅分別為588 mV/decade和196 mV/decade，由載子遷移率比較中可得知三閘極奈米線薄膜電晶體因成功避開晶粒邊界之影響，使得伸張應變有效提升電子遷移率，同時亦因擁有較佳的閘極控制能力，使得次臨界擺幅表現上優於平面式薄膜電晶體，在另一方面，我們也利用連續波雷射製備高性能P型三閘極奈米線極薄膜電晶體，其載子遷移率、次臨界擺幅和臨界電壓分別為217 cm2V-1s-1、283 mV/decade、-1.71 V，然而在這邊伸張應變對於P型元件電特性之效應較不明顯，由先前相關研究指出，因單軸之伸張應變對於P型元件之電特性較無增強之作用，最後藉由探討操作溫度對於元件載子遷移率之影響，證明連續波雷射結晶多晶矽三閘極奈米線電晶體擁有類單晶之特性。 本論文已成功探討利用連續波雷射結晶製備高性能三閘極應變多晶矽奈米線薄膜電晶體，而此元件未來在系統面板(System on Panel)及三維積體電路(Three-Dimensional Integrated Circuits)之應用將擁有相當大的發展潛力。

Low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have been widely used in active matrix flat panel displays (AMFPDs), since they demonstrated much higher field-effect mobility and lower power consumption than the conventional amorphous silicon (α-Si) TFTs. There were several technologies for LTPS thin films, including solid phase crystallization (SPC), metal-induced crystallization (MIC), metal-induced lateral crystallization (MILC), excimer laser crystallization (ELC), and continuous wave laser crystallization (CLC). These approaches all could effectively transform the α-Si thin films as the polycrystalline silicon (poly-Si) thin films. Among these technologies, the grain size of poly-Si thin films fabricated by the CLC was the biggest. In addition, the CLC poly-Si thin films possessed the excellent crystallinity and flat surface morphology. Thus, the CLC poly-Si TFTs usually could demonstrate high performance and superior reliability. According to the previous researches, it was also found that the CLC poly-Si thin films possessed biaxial tensile strain which could effectively improve the carrier mobility. To realize such an effect and observe the mobility enhancement for the CLC poly-Si TFTs, the spacer technology to obtain nanowire structures was applied to avoid the grain boundaries. At first, the material analysis for the CLC poly-Si thin films was investigated. The CLC poly-Si thin films possessed the grain size of 2 μm* 20 μm, flat surface morphology, excellent crystallinity, and the induced thermal stress of about 800 MPa. Meanwhile, the phenomenon of strain relaxation by the pattern effect was also discussed here. The results indicated that the biaxial tensile strain in the CLC poly-Si thin films would become uniaxial tensile strain when the CLC poly-Si thin films were patterned as the CLC poly-Si nanowires. In the second part, the electrical characteristics of the CLC poly-Si TFTs were studied. First, the comparisons of electrical characteristics between the planar CLC poly-Si TFTs and the tri-gate CLC poly-Si NW TFTs would be conducted. The results presented that the planar CLC poly-Si TFTs with L/W = 2μm/ 1μm attained the μFE of 625 cm2V-1s-1, subthreshold swing (S.S.) of 588 mV/decade, threshold voltage (Vth) of -3 V. In contrast, the tri-gate CLC poly-Si NW TFTs with L/Weff = 2μm/ 1μm achieved the μFE of 825 cm2V-1s-1, S.S. of 196 mV/decade, and Vth of -1 V. It was observed that the tri-gate CLC poly-Si NW TFTs demonstrated much better performance than the planar ones owing to the strain enhancement, better crystallinity, and better gate control ability. The tri-gate CLC poly-Si NW TFTs successfully avoided the grain boundaries in the channel regions of the devices. On the other hand, the p-type tri-gate CLC poly-Si NW TFTs with L/Weff = 3 μm/ 4 μm also achieved μFE of 217 cm2V-1s-1. The strain enhancement for the p-type devices was not so obvious. According to previous researches, it was found that the uniaxial tensile strain was not helpful for improving the hole mobility. Finally, the dependence of μFE on the temperature for the tri-gate CLC poly-Si NW TFTs was also examined. The results indicated that the tri-gate CLC poly-Si NW TFTs exhibited the single-grain-like characteristics. The high-performance tri-gate TFTs with the strained poly-Si NWs via the CLC have been successfully fabricated to be promising for the application in the future system on a panel (SOP) and three-dimensional integrated circuits (3D-ICs).