應用於可程式閘陣列之多埠記憶體設計

Full metadata record

DC Field	Value	Language
dc.contributor.author	林俊良	en_US
dc.contributor.author	Lin, Jiun-Liang	en_US
dc.contributor.author	賴伯承	en_US
dc.contributor.author	Lai, Bo-Cheng	en_US
dc.date.accessioned	2015-11-26T01:02:00Z	-
dc.date.available	2015-11-26T01:02:00Z	-
dc.date.issued	2015	en_US
dc.identifier.uri	http://140.113.39.130/cdrfb3/record/nctu/#GT070250242	en_US
dc.identifier.uri	http://hdl.handle.net/11536/127121	-
dc.language.iso	en_US	en_US
dc.subject	可程式閘陣列	zh_TW
dc.subject	多埠記憶體	zh_TW
dc.subject	有效的使用嵌入式區塊記憶體	zh_TW
dc.subject	平行	zh_TW
dc.subject	FPGA	en_US
dc.subject	multi-ported memory	en_US
dc.subject	BRAM efficient	en_US
dc.subject	Parallel	en_US
dc.title	應用於可程式閘陣列之多埠記憶體設計	zh_TW
dc.title	Efficient Designs of Multi-ported Memory on FPGA	en_US
dc.type	Thesis	en_US
dc.contributor.department	電子工程學系電子研究所	zh_TW
Appears in Collections:	Thesis