28 奈米高介電係數金屬閘極製程操縱在 近/次臨界電壓之256kb 6T 靜態隨機存取記憶體

Abstract

近年來，由於靜態隨機存取記憶體具有較快的存取速度，主要被廣泛應用在高效能的處理器以及嵌入式系統中的快取記憶體。簡單的架構、快速的操作速度以及高容量密度的優勢，傳統的6T靜態隨機存取記憶體因而被廣泛地使用。隨著穿戴式裝置產品的發展與物聯網概念的興起，低功率消耗、低操作電壓的電路逐漸成為今日SoC晶片設計的趨勢。然而，在先進技術中，傳統的6T靜態隨機存取記憶體因製成的變異所以讀寫能力嚴重退化，使其難以在低電壓中正常操作。 本篇論文提出一個新的6T靜態隨機存取記憶體迷你陣列架構，並搭配所提出的轉換電壓協助寫入技術以增加6T靜態隨機存取記憶體的寫入能力。迷你陣列架構使用晶圓廠標準的6T靜態隨機存取記憶體細胞在犧牲少量的額外面積的情況下，大幅降低6T操作電壓至近/次臨界電壓。為了低功率消耗電路應用，我們也提出了電源控制與低擺幅預充電器搭配大訊號感測技術。利用本篇中所提出的技術，我們設計出一顆容量為256kb，可操作在近/次臨界電壓的6T靜態隨機存取記憶體電路，並透過下線實現在聯電28奈米高介電係數金屬閘極半導體製程上。測試晶片的面積是1058 x 374微米平方，測量的工作電壓範圍可以涵蓋0.9V到0.4V，在0.9V，常溫25度C下，電路工作頻率最高可以達到866MHz。

In recent years, SRAMs are widely used as cache memory in high performance processor and embedded system. Because of the advantages of simple structure, high operation speed and high capacity density, the conventional 6T SRAM is the most widely used. With wearable devices and Internet of Things (IoT) is currently on the rise, Low-Power and Low-Voltage circuit design becomes a major trend in SoCs (System-On-Chip) nowadays. However, conventional 6T SRAM is hardly used to operate in low voltage due to severe read/write ability degradation in advanced process. This thesis presents a novel 6T Mini-array architecture with Vtrip tracing write assist (VTWA) to improve the write-ability. The Architecture can be operated with near/sub-threshold voltage. For low power application, we propose the Power-gating structure, and integrated low-swing voltage pre-charger with large-signal sensing scheme. The proposed near/sub-threshold 6T SRAM is demonstrated by a 1058 x 374 μm2 256kb SRAM macro in UMC 28nm high-k metal-gate (HKMG) CMOS technology. The full functionality is error-free under operating voltage from 0.9V to 0.4V. The measured maximum operation frequency is 866MHz at 0.9V, TT corner, 25℃.