應用於人工電子耳之低功耗、低失真前置放大器

Abstract

對於聽障患者而言，能夠恢復聽覺是他們長期的夢想。隨著人工電子耳的發明，聽障患者能夠藉由植入輔具-人工電子耳，並配合術後的訓練，幫助他們重新察覺環境聲音，獲得更好的語言理解力並增進溝通的能力，使他們重回有聲世界。 本篇主旨為提出一應用於人工電子耳系統之全差動前置放大電路，目的用以濾除非音頻訊號並放大，使音頻訊號得以被凸顯。在子電路上設計，為了將非理想成份諸如閃爍雜訊、熱雜訊等消除，提高其訊號雜訊比，以增加音頻訊號之可辨度，本電路採用全差動雙級運算放大器，並藉由設計電晶體尺寸來抑制雜訊，將輸入級的場效電晶體操作於弱反轉區，以此降低電路在低頻產生的閃爍雜訊並降低電路的功率消耗。考量到處理音頻訊號的系統設計上，群延遲將對音頻訊號造成影響，不同頻率下的訊號有不同的延遲時間將會造成音頻訊號失真，因此將系統頻寬設計為10Hz至200kHz以確保欲保留的100Hz至20kHz音頻訊號不受影響。針對產生極低頻極點需要的大電阻，在兩個架構中分別並使用虛擬電阻與交換電容器電阻來實現，以解決傳統大電阻、電容造成的面積消耗問題。整體電路以高解析度、低功耗及低雜訊為設計目標，以符合生醫電子系統之效能要求。 本文所提整體前置放大電路之頻寬設計為10Hz至200kHz，將增益設計為1倍、1.5倍、2倍、6倍的可調倍率。在電路實現上，當輸入訊號頻率1kHz、0.45V輸入振幅、系統增益1倍的情況下，兩個架構之整體總諧波失真率加雜訊(THD+N)分別為-81dB與-82dB。本電路使用TSMC 0.18μm標準CMOS 1P6M製程完成，其晶片面積分別為0.7mm^2與2.68mm^2。在1.8 V電源供應下，總功率消耗分別約為42μW與173μW。

For deaf people, to restore hearing is their long-term goals. The invention of cochlear implant, which is an auxiliary device implanted in the inner ear, can offer the sense of the sound to deaf people by electrical stimulation. After post-operative training, they will be able to perceive environmental sounds, obtain better verbal comprehension, and improve communication abilities. This thesis presents fully differential preamplifiers for cochlear prosthesis application that can reduce effect of noise and amplify signals in the audio band. The non-ideal effects, such as the flicker noise and thermal noise, have been considered in the design of the fully differential two-stage OPAMP. The signal-to-noise ratio (SNR) of the proposed preamplifier is improved and this preamplifier offers a high resolution for the audio signals. Designing the input pair of the first stage in the weak-inversion region can reduce the low-frequency noise and power consumption in the two-stage OPAMP. The proposed preamplifier is applied for audio application, so the group delay is needed to take into account in design. In view of the group delay, the system bandwidth is designed from 10 Hz to 200 kHz to ensure that the audio signals from 100 Hz to 20 kHz have the same group delay. In order to achieve the first pole at 10 Hz, the systems need a huge resistor or capacitor which cost a lot of chip area. The resistors applied in the preamplifier are implemented by pseudo-resistor and switched-capacitor resistor, respectively. The passband bandwidth of the proposed system is designed from 10 Hz to 200 kHz and the programmable gain of the system is designed as 15.6/6/3.5/0 dB. When the gain is 0 dB, the total harmonic distortion plus noise (THD+N) of two architectures is -81 dB and -82 dB for 1 kHz input frequency, respectively. The proposed systems have been designed and fabricated by standard 0.18 µm CMOS process in chip areas of 0.7 mm^2 and 2.68 mm^2. The power dissipation is 42μW and 173 µW from a 1.8 V supply, respectively.