電阻式記憶體操作後導致缺陷產生與寫入干擾錯誤時間劣化之研究

Abstract

在本篇論文中，我們針對電阻式記憶體在寫入/抹除操作後導致缺陷產生與寫入干擾錯誤所需時間之劣化現象做討論。藉由量測元件的漏電流並分析其傳導特性，我們證明元件在定電壓應力及寫入/抹除週期應力操作下皆會造成介電層中的缺陷產生。我們進一步探討新產生的缺陷與寫入干擾錯誤所需時間之劣化現象的關聯，發現造成此劣化現象的原因是由於新產生的缺陷有助形成更易導通的路徑。最後，我們利用以滲透理論為基礎建立的解析模型成功地描述實驗上發生此劣化現象所需應力時間的統計分佈。

In this thesis, cycling stress induced trap creation and write disturb failure time degradation mode are investigated by analyzing the carrier transport properties of the leakage current. The results reveal that stress-induced traps will generate in an RRAM dielectric after constant voltage stress test or cycling stress test. The correlation between stress-induced traps and write disturb failure time degradation is further discussed. It is observed that write disturb failure time degradation is caused by the formation of a new conducting path which is related to the stress-induced traps. Finally, an analytical model based on the percolation concept of oxide breakdown can well explain the statistical distribution of the stress time which is needed to induce write disturb failure time degradation.