零時和時間依賴引致臨界電壓改變量分布在奈米線結構無接面電晶體

Abstract

無接面電晶體的電性表現和傳統的翻轉層電晶體可以視為一致，但是在物理機制上，兩者是截然不同的。本篇論文，我們將利用完整的3D模擬軟體來觀察無接面半導體和傳統電晶體在大量統計下的變化、可靠度議題。 第二章探討大量統計下臨界電壓、臨界電壓變異數和隨機的離散摻雜兩者之間的關係。被指出，由於較嚴重摻雜變異，使臨界電壓變異數的變化幅度在無接面電晶體較為嚴重。 然後，我們研究隨機介面缺陷、隨機離散摻雜分別在無接面電晶體和傳統的電晶體所造成統計分布的改變。研究結果顯示大量統計下，主要分布會幾乎重合；此外，傳統翻轉層電晶體更容易受制於表面缺陷的影響。最後，我們分析這些現象，並提出合理的解釋。

The electrical characteristics of junctionless (JL) transistors are identical to those of traditional transistors, but the physics is entirely different. In this thesis, a comprehensive full-scale 3D simulation study of statistical variability and reliability in junctionless (JL) nanowire and inversion mode (IM) nanowire transistors are discussed. We investigate the statistical threshold voltage and threshold voltage variations associated with random discrete dopants (RDD). It is pointed out that Vth is more significant in JL NW due to dopant fluctuation effect.

Then, we study the statistical distribution associated with random interface trap (RIT) and RDD in both JL and IM transistors. The results show that the main distributions in JL and IM are overlapped. Moreover, IM transistors are prone to the influence of the defect in the interface. In the end, we analyze these phenomena by proposing a reasonable explanation.