雙頻帶和寬頻源級退化電感低雜訊放大器雜訊的最佳化設計

Abstract

本論文研討源級退化低雜訊放大器具雙頻帶及寬頻帶輸入匹配網路的最佳化設計方法，首先，本論文說明及介紹雜訊描述的表示法、雙埠網路雜訊參數的Thevenin與Norton形式及其對應的互換關係式，再者，本論文簡述電晶體的雜訊參數。 基於已知的單頻帶源級退化低雜訊放大器雙埠雜訊參數理論，本論文經由模擬的定性分析將其推廣應用設計最佳化雙頻帶及寬頻帶的低雜訊放大器設計。在雙頻帶低雜訊放大器的部分，本論文藉由模擬的方式來討論損耗的效應於前端晶片電感匹配網路，當晶片電感為無損時，最低的雜訊指數(Noise figure minimum, NFmin)呈現一斜直線，而當晶片電感為有損時，則會產生一突起點．因此本論文探討如何選擇適當的電晶體尺寸及輸入匹配來達到最佳化的雙頻帶低雜訊放大器設計．最後，本論文實現兩2.4/5GHz共存式雙頻帶低雜訊放大器於TSMC 0.18μm CMOS與0.18μm SiGe BiCMOS製程實現，並討論實際量測結果來驗證設計的最佳化分析。 另一方面，本論文探討使用柴比雪夫濾波器做為輸入匹配的寬頻源級退化低雜訊放大器設計，本論文亦根據輸入端的晶片電感並利用模擬方式來探討其對雜訊指數的影響並藉此提出一個定性的最佳化設計理論．本論文提出針對輸入匹配及雜訊特性為主的兩種設計方式，並實作兩種3~8 GHz寬頻低雜訊放大器於TSMC 0.18μm CMOS製程，並討論實際量測結果。

This thesis studies the design optimization of inductively source degenerated low-noise amplifier (LNA) with dual-band and broadband input networks. At first, this thesis introduces the noise expression of two-port noise parameters in Thevenin and Norton formats and the corresponding transformation. Then, this thesis introduces the two-port noise parameters of MOSFET. Based on the well-known noise parameters of MOSFET and single-band inductively source degenerated LNA, this thesis can extend to discuss noise behavior of dual-band and broadband input networks by simulation according to qualitative analysis. For the dual-band LNA design, this thesis discusses loss effect in input on-chip inductors by simulation. When the on-chip input inductors are lossless, the noise figure minimum (NFmin) performs a monotonic increasing. When the loss effect is taken into consideration, it has a spike between two operating bands. Therefore, this thesis develops a design methodology to select optimal device width and input inductance and capacitance to achieve good noise performance. Finally, this thesis demonstrates two 2.4/5 GHz concurrent dual-band LNAs using TSMC 0.18μm CMOS and 0.18μm SiGe BiCMOS, respectively. The presented design optimization method can be proved and agreed with measured result. On the other hand, this thesis also studies the design optimization method of an inductively source degenerated LNA with a broadband input network. This Thesis also follows qualitative analysis to establish the design optimization method according to simulated results between lossless and lossy input networks. This thesis demonstrates two broadband LNAs using LC-ladder input network while the first LNA focuses on input match and the second LNA focuses on noise performance, respectively. Two broadband LNAs are demonstrated around of 3~8 GHz using TSMC 0.18μm CMOS technology to discuss noise behavior and validate the presented design method.