Spacer之設計對多重閘極絕緣砷化銦鎵金氧半鰭狀式場效電晶體的靜電完整性及效能的影響

Abstract

這篇論文藉由TCAD模擬探討spacer設計對於多重閘極自我對準源/汲極絕緣砷化鎵銦金氧半鰭狀式場效電晶體的影響。我們的研究指出vacuum spacer可以藉由降低汲極穿透電場來降低使用高介電常數閘極介電層所造成的靜電完整性劣化現象。元件使用高介電常數閘極介電層時，vacuum spacer因為有較小的邊際電容以及較大的啟動電流因此有較佳的反流器延遲。除此之外，我們也探討了vacuum spacer對於6T靜態隨機存取記憶體的穩定性跟效能的影響。然而當元件源極跟汲極介面遠離閘極控制區時，vacuum spacer比起nitride spacer會有更大的源極阻抗。我們的研究指出corner spacer可以用來降低源極阻抗以及維持較小的邊際電容因此會有較好的反流器延遲。除此之外，絕緣砷化鎵銦金氧半鰭狀式場效電晶體使用corner spacer時會跟使用vacuum spacer具備相近的靜電完整性。

This thesis investigates the impacts of spacer design for multi-gate InGaAs-OI FinFETs with self-aligned contact using TCAD simulations. Our study indicates that vacuum spacer can mitigate the degradation of electrostatic integrity induced by higher-k gate dielectric because of the reduction of drain field penetration. High-k devices with vacuum spacer also shows better inverter delay due to smaller fringing capacitance and larger ON current. In addition, the impacts of vacuum spacer on the stability and performance of 6T-SRAM are also investigated. However, source/drain-underlap devices with vacuum spacer suffer from larger source resistance compared to the nitride-spacer counterparts. Our study indicates that the use of corner spacer can reduce the source resistance, maintain smaller fringing capacitance, and result in better inverter delay. In addition, the InGaAs-OI FinFET with corner-spacer design possesses similar electrostatic integrity to the all-vacuum spacer counterpart.