标题: An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability
作者: Yang, Chi-Heng
Lin, Yi-Min
Chang, Hsie-Chia
Lee, Chen-Yi
电子工程学系及电子研究所
Department of Electronics Engineering and Institute of Electronics
关键字: Bose-Chaudhuri-Hocquenghem (BCH) codes;encoder;error correcting codes (ECC);NAND flash;syndrome
公开日期: 1-七月-2015
摘要: This paper presents an area-efficient architecture of arbitrary error correction Bose-Chaudhuri-Hocquenghem codec for NAND flash memory. By factorizing the generator polynomial into several minimal polynomials and utilizing linear feedback shift registers based on minimal polynomials, our reconfigurable design cannot only support multiple error correcting capabilities at a few extra cost, but also merge the encoder and syndrome calculator for efficiently reducing hardware complexity. After being implemented in CMOS 65-nm technology, the test chip supporting t = 1-24 bits can achieve 1.33-Gb/s measured throughput with 73k gate-count while another design supporting t = 60-84 bits can provide 1.60-Gb/s synthesized throughput with 168.6k gate-count.
URI: http://dx.doi.org/10.1109/TVLSI.2014.2338309
http://hdl.handle.net/11536/127873
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2014.2338309
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 23
起始页: 1235
结束页: 1244
显示于类别:Articles