標題: Impact of V-pass Interference on Charge-Trapping NAND Flash Memory Devices
作者: Hsiao, Yi-Hsuan
Lue, Hang-Ting
Chen, Wei-Chen
Chang, Kuo-Pin
Tsui, Bing-Yue
Hsieh, Kuang-Yeu
Lu, Chih-Yuan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: SONOS;Charge-trapping;fringing field;interference;pass gate voltage
公開日期: 1-Jun-2015
摘要: The impact of adjacent word-line\'s pass gate voltage interference on charge-trapping (CT) NAND Flash is extensively studied in this paper. From our previous work with a 38-nm half-pitch BE-SONOS NAND Flash device, we found that the threshold voltage significantly decreases with increasing pass gate voltage during reading. This observation is in contrary to the common belief that the CT NAND devices are immune to interference. In this paper, we further evaluate the pass gate voltage interference on 3-D CT NAND Flash, which is the most promising path for the future NAND Flash industry. Owing to the superior gate control ability in the double-gate architecture, the commonly observed pass gate voltage interference due to pitch scaling is suppressed. Stronger gate control ability also restrains the impact of field penetration in devices with narrow channel width. In 3-D CT NAND Flash, the thinner channel can also provide better gate control ability, which, in turn, results in smaller pass gate voltage interference.
URI: http://dx.doi.org/10.1109/TDMR.2015.2398193
http://hdl.handle.net/11536/127916
ISSN: 1530-4388
DOI: 10.1109/TDMR.2015.2398193
期刊: IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
Volume: 15
起始頁: 136
結束頁: 141
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