標題: An Automatic Synthesis Tool for Nanometer Low Dropout Regulator Using Simulation Based Model and Geometric Programming
作者: Hsu, Shih-Hsin
Chen, Wei-Zen
Zheng, Jui-Pin
Liu, Sean S. -Y.
Pan, Po-Cheng
Chen, Hung-Ming
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Jan-2014
摘要: This paper presents an efficient synthesis framework for Low Dropout Regulator (LDOs) automatic design to facilitate varieties of power management ICs applications. A four-stage synthesizer is proposed to deal with topology selection, transistor sizing, and layout generation automatically. The proposed approach correctly describes device behaviors in moderate and strong inversion regions for current optimization. Without trivial trial and error procedure, the "SPICE accuracy" device size mapping is provided, and the resulting layout is compact and regular while meeting analog design constraints. Using the proposed synthesis tool for LDO automatic design, a prototype chip has been successfully fabricated in 65nm CMOS process. The experimental results validate our methodology in industrial cases with high performance and meet all the target specifications.
URI: http://hdl.handle.net/11536/128471
ISBN: 978-1-4799-2776-0
ISSN: 
期刊: 2014 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)
Appears in Collections:Conferences Paper