Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yu, Yung-Hui | en_US |
dc.contributor.author | Wang, Po-Hao | en_US |
dc.contributor.author | Chen, Tien-Fu | en_US |
dc.contributor.author | Lin, Tay-Jyi | en_US |
dc.contributor.author | Wang, Jinn-Shyan | en_US |
dc.date.accessioned | 2015-12-02T03:00:50Z | - |
dc.date.available | 2015-12-02T03:00:50Z | - |
dc.date.issued | 2014-01-01 | en_US |
dc.identifier.isbn | 978-1-4799-3773-8 | en_US |
dc.identifier.issn | en_US | |
dc.identifier.uri | http://hdl.handle.net/11536/128481 | - |
dc.description.abstract | Scaling down the supply voltage for embedded SoC becomes a necessary technique to lower power requirements in mobile devices. However, caches become susceptible or even fail in low voltages, and distribution of access latencies is significantly increased in new technology nodes. Past researches suggested several solutions to deal with the memory reliability at low voltages, where a timing table records cache lines with latency faults. This paper proposes cache management strategies for variable-latency caches at low voltages. We analyze the locality effect and propose two methods to dynamically adapt latency faults at run time and give the advantages of those methods compared to traditional LRU for low-voltage caches. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | variable-latency cache | en_US |
dc.subject | low-voltage cache | en_US |
dc.subject | timing fault | en_US |
dc.subject | cache management | en_US |
dc.title | Adaptive Variable-Latency Cache Management for Low-Voltage Caches | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2014 IEEE FAIBLE TENSION FAIBLE CONSOMMATION (FTFC) | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000356507700011 | en_US |
dc.citation.woscount | 0 | en_US |
Appears in Collections: | Conferences Paper |