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dc.contributor.authorYu, Yung-Huien_US
dc.contributor.authorWang, Po-Haoen_US
dc.contributor.authorChen, Tien-Fuen_US
dc.contributor.authorLin, Tay-Jyien_US
dc.contributor.authorWang, Jinn-Shyanen_US
dc.date.accessioned2015-12-02T03:00:50Z-
dc.date.available2015-12-02T03:00:50Z-
dc.date.issued2014-01-01en_US
dc.identifier.isbn978-1-4799-3773-8en_US
dc.identifier.issnen_US
dc.identifier.urihttp://hdl.handle.net/11536/128481-
dc.description.abstractScaling down the supply voltage for embedded SoC becomes a necessary technique to lower power requirements in mobile devices. However, caches become susceptible or even fail in low voltages, and distribution of access latencies is significantly increased in new technology nodes. Past researches suggested several solutions to deal with the memory reliability at low voltages, where a timing table records cache lines with latency faults. This paper proposes cache management strategies for variable-latency caches at low voltages. We analyze the locality effect and propose two methods to dynamically adapt latency faults at run time and give the advantages of those methods compared to traditional LRU for low-voltage caches.en_US
dc.language.isoen_USen_US
dc.subjectvariable-latency cacheen_US
dc.subjectlow-voltage cacheen_US
dc.subjecttiming faulten_US
dc.subjectcache managementen_US
dc.titleAdaptive Variable-Latency Cache Management for Low-Voltage Cachesen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 IEEE FAIBLE TENSION FAIBLE CONSOMMATION (FTFC)en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000356507700011en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper