The CMP process and cleaning solution for planarization of strain-relaxed SiGe virtual substrates in MOSFET applications

doi:10.1149/1.2149291

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DC 欄位	值	語言
dc.contributor.author	Shieh, MS	en_US
dc.contributor.author	Chen, PS	en_US
dc.contributor.author	Tsai, MJ	en_US
dc.contributor.author	Lei, TF	en_US
dc.date.accessioned	2014-12-08T15:17:43Z	-
dc.date.available	2014-12-08T15:17:43Z	-
dc.date.issued	2006	en_US
dc.identifier.issn	0013-4651	en_US
dc.identifier.uri	http://hdl.handle.net/11536/12859	-
dc.identifier.uri	http://dx.doi.org/10.1149/1.2149291	en_US
dc.description.abstract	The effects of different polishing pads and slurry solid contents on the SiGe chemical mechanical polish (CMP) process were investigated. By optimizing the polishing conditions, a smooth strained-Si surface on a flattened Si0.8Ge0.2 buffer layer of 0.6 nm can be achieved. The novel cleaning solutions with various surfactants and chelating agents for post-CMP SiGe were studied. There was about 10% current enhancement of the optimal cleaning conditions, showing high performance in particle removal, metallic cleaning, and electrical characteristics. (c) 2005 The Electrochemical Society.	en_US
dc.language.iso	en_US	en_US
dc.title	The CMP process and cleaning solution for planarization of strain-relaxed SiGe virtual substrates in MOSFET applications	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1149/1.2149291	en_US
dc.identifier.journal	JOURNAL OF THE ELECTROCHEMICAL SOCIETY	en_US
dc.citation.volume	153	en_US
dc.citation.issue	2	en_US
dc.citation.spage	G144	en_US
dc.citation.epage	G148	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000234543400063	-
dc.citation.woscount	4	-
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