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dc.contributor.authorChou, Fang-Tingen_US
dc.contributor.authorChen, Chia-Minen_US
dc.contributor.authorChen, Zong-Yien_US
dc.contributor.authorHung, Chung-Chihen_US
dc.date.accessioned2015-12-02T03:00:57Z-
dc.date.available2015-12-02T03:00:57Z-
dc.date.issued2014-01-01en_US
dc.identifier.isbn978-1-4799-5230-4en_US
dc.identifier.issnen_US
dc.identifier.urihttp://hdl.handle.net/11536/128600-
dc.description.abstractThis paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic range (SFDR) has been improved over 10dB compared to the conventional DAC without variable-delay buffers. This chip was implemented in a standard 0.18um CMOS technology, occupies 1.1mm(2) core area, and dissipates 19mW from a single 1.8V power supply.en_US
dc.language.isoen_USen_US
dc.subjectDACen_US
dc.subjectBinary-weighteden_US
dc.subjectvariable-delay bufferen_US
dc.titleA Novel Glitch Reduction Circuitry for Binary-Weighted DACen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)en_US
dc.citation.spage240en_US
dc.citation.epage243en_US
dc.contributor.department電機資訊學士班zh_TW
dc.contributor.departmentUndergraduate Honors Program of Electrical Engineering and Computer Scienceen_US
dc.identifier.wosnumberWOS:000361128200058en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper