標題: Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC
作者: Chou, Fang-Ting
Hung, Chung-Chih
電機學院
College of Electrical and Computer Engineering
關鍵字: Binary weighted;current switch;digital-to-analog converter (DAC);dynamic capacitance;glitch energy
公開日期: 六月-2016
摘要: This brief proposes a glitch reduction approach by dynamic capacitance compensation of binary-weighted current switches in a current-steering digital-to-analog converter (DAC). The method was proved successfully by a 10-bit 400-MHz pure binary-weighted current-steering DAC with a minimum number of retiming latches. The experiment results yield very low-glitch energy during major carry transitions at output, which is <1 pVs. This brief utilizes a layout structure to improve the spurious-free dynamic range at high signal frequencies. This chip was implemented in a standard 0.18-mu m CMOS technology and consumes 20.7 mW at 400 MS/s.
URI: http://dx.doi.org/10.1109/TVLSI.2015.2503727
http://hdl.handle.net/11536/134033
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2015.2503727
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 24
Issue: 6
起始頁: 2407
結束頁: 2411
顯示於類別:期刊論文