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dc.contributor.authorHWANG Weien_US
dc.contributor.authorWANG Dao-Pingen_US
dc.date.accessioned2015-12-04T07:03:10Z-
dc.date.available2015-12-04T07:03:10Z-
dc.date.issued2015-06-18en_US
dc.identifier.govdocG11C011/412zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/128671-
dc.description.abstractA multi-port SRAM with shared write bit-line architecture and selective read path for low power operation includes a first memory cell, a second memory cell, and a common switch set. The second memory cell makes use of the common switch set to share the A-port write bit-line and the B-port write bit-line with the first memory cell so as to reduce half write bit-line number and reduce the write current consumption caused by pre-charging the bit-line to VDD. It also provides a selective read path structure for read operation. Replacing the ground connection in the read port with a virtual VSS controlled by a Y-select signal reduces read-port current consumption.zh_TW
dc.language.isozh_TWen_US
dc.titleMULTI-PORT SRAM WITH SHARED WRITE BIT-LINE ARCHITECTURE AND SELECTIVE READ PATH FOR LOW POWER OPERATIONzh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber20150170734zh_TW
Appears in Collections:Patents


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