完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Jiang, IHR | en_US |
dc.contributor.author | Pan, SR | en_US |
dc.contributor.author | Chang, YW | en_US |
dc.contributor.author | Jou, JY | en_US |
dc.date.accessioned | 2014-12-08T15:17:44Z | - |
dc.date.available | 2014-12-08T15:17:44Z | - |
dc.date.issued | 2006-01-01 | en_US |
dc.identifier.issn | 1084-4309 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1016/j.tsf.2005.12.184 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/12874 | - |
dc.description.abstract | As technology advances apace, crosstalk becomes a design metric of comparable importance to area and delay. This article focuses mainly on the crosstalk issue, specifically on the impacts of physical design and process variation on crosstalk. While the feature size shrinks below 0.25 mu m, the impact of process variation on crosstalk increases rapidly. Hence, a crosstalk insensitive design is desirable in the deep submicron regime. In this article, crosstalk sensitivity is referred to as the influence of process variation on crosstalk in a circuit. We show that the lower bound of crosstalk sensitivity grows quadratically, while that of crosstalk increases linearly. Therefore, designers should also consider crosstalk sensitivity, when optimizing other design objectives such as crosstalk, area, and delay. According to our modeling, these objectives are all in posynomial forms, and thus the multiobjective optimization problem can optimally be solved by Lagrangian relaxation. Experimental results show that our method is effective and efficient. For instance, a circuit of 2856 gates and 5272 wires is optimized using 13-minute runtime and 2.8-MB memory on a Pentium III 1.0 GHz PC with 256-MB memory. In particular, by relaxing Lagrange multipliers to the critical paths, it takes only two iterations for all solutions to converge to the global optimal, which is much more efficient than related previous work. This relaxation scheme provides a key insight into the rapid convergence in Lagrangian relaxation. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | algorithms | en_US |
dc.subject | performance | en_US |
dc.subject | VLSI | en_US |
dc.subject | interconnect | en_US |
dc.subject | post-layout optimization | en_US |
dc.subject | lagrangian relaxation | en_US |
dc.title | Reliable crosstalk-driven interconnect optimization | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1016/j.tsf.2005.12.184 | en_US |
dc.identifier.journal | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS | en_US |
dc.citation.volume | 11 | en_US |
dc.citation.issue | 1 | en_US |
dc.citation.spage | 88 | en_US |
dc.citation.epage | 103 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000236871100006 | - |
dc.citation.woscount | 1 | - |
顯示於類別: | 期刊論文 |