標題: A Long Block Length BCH Decoder for DVB-S2 Application
作者: Lin, Yi-Min
Wu, Jau-Yet
Lin, Chien-Ching
Chang, Hsie-Chia
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2009
摘要: In this paper, a low-complexity and full-mode BCH decoder with long block length for DVB-S2 application is presented. With the reversed error locator polynomial, our proposed reversed Berlekamp-Massey algorithm features a sharing architecture to perform parallel-4 syndrome and Chien search calculations. Concatenated with the LDPC decoder, which has a long decoding latency and a short period of data output time, the proposed parallel-4 BCH decoder ensures the sufficient throughput with only one bank memory. Moreover, a composite field divider instead of a large Galois field inversion table is also presented to reduce complexity. After implemented in 0.13 mu m CMOS technology, our parallel-4 BCH decoder occupied 44K gate count can reach 380Mb/s according to the post-layout simulations.
URI: http://hdl.handle.net/11536/12934
ISBN: 978-981-08-2468-6
期刊: PROCEEDINGS OF THE 2009 12TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC 2009)
起始頁: 300
結束頁: 303
顯示於類別:會議論文