標題: A Novel Flexible 3-D Heterogeneous Integration Scheme Using Electroless Plating on Chips With Advanced Technology Node
作者: Hu, Yu-Chen
Lin, Chun-Pin
Chang, Yao-Jen
Chang, Nien-Shyang
Sheu, Ming-Hwa
Chen, Chi-Shi
Chen, Kuan-Neng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: 3-D integration;heterogeneous
公開日期: 1-Dec-2015
摘要: A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node.
URI: http://dx.doi.org/10.1109/TED.2015.2487041
http://hdl.handle.net/11536/129354
ISSN: 0018-9383
DOI: 10.1109/TED.2015.2487041
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 62
Issue: 12
起始頁: 4343
結束頁: 4348
Appears in Collections:Articles