標題: Microwave and Millimeter-Wave CMOS Frequency Doubler and Tripler Designs
作者: Wu, Kun-Long
Tsai, Han-Ting
Tseng, Pei-Ling
Hu, Robert
Jou, Christina F.
Shiao, Yu-Shao
交大名義發表
National Chiao Tung University
公開日期: 1-一月-2014
摘要: This manuscript describes our 17.4GHz 0.18 mu m-CMOS doubler and 77GHz 65nm-CMOS tripler designs. For the doubler, attention has been made on effectively suppressing the fundamental, third and forth harmonics using LLC filtering networks and balun. As for the tripler, the unwanted second-order harmonic can be suppressed through the use of large source impedance on the differential pair while the fundamental signal leakage is removed by an embedded notch filter; therefore, the intended third-harmonic output is almost 40dB larger than all the other spurious signals. The tripler chip size is 700x940um, and it consumes 93mW under 1.2V bias; the 3dB bandwidth for output is 9GHz.
URI: http://hdl.handle.net/11536/129811
ISBN: 978-1-4673-5225-3
ISSN: 
期刊: 2014 XXXITH URSI GENERAL ASSEMBLY AND SCIENTIFIC SYMPOSIUM (URSI GASS)
顯示於類別:會議論文