Microwave and Millimeter-Wave CMOS Frequency Doubler and Tripler Designs

Abstract

This manuscript describes our 17.4GHz 0.18 mu m-CMOS doubler and 77GHz 65nm-CMOS tripler designs. For the doubler, attention has been made on effectively suppressing the fundamental, third and forth harmonics using LLC filtering networks and balun. As for the tripler, the unwanted second-order harmonic can be suppressed through the use of large source impedance on the differential pair while the fundamental signal leakage is removed by an embedded notch filter; therefore, the intended third-harmonic output is almost 40dB larger than all the other spurious signals. The tripler chip size is 700x940um, and it consumes 93mW under 1.2V bias; the 3dB bandwidth for output is 9GHz.